Search

This paper presents a coupled electromagnetic and thermal design methodology which addresses the problem of balancing accuracy against computation time. A case study on a short-duty permanent-magnet (PM) linear actuator is used to illustrate the approach. The proposed method employs a two-dimensional electromagnetic finite-element (FE) model coupled with a detailed thermal equivalent circuit (TEC) model which is automatically constructed and parameterized using geometric and material data. A numerical method of estimating the equivalent thermal properties of the winding amalgam is used along with published empirically derived convection and radiation heat transfer correlations. The relatively high number of network nodes and more accurate thermal material properties minimizes model calibration and allows improved temperature prediction, including winding hot spots, while maintaining a low computational cost for both steady-state and transient analyses. A comparison between experimental and theoretical actuator performance shows that the design methodology provides good accuracy electromagnetic and transient thermal performance predictions without the need for direct model calibration and can yield an optimized design within an acceptable time frame. [ABSTRACT FROM PUBLISHER]

Yield optimization is a challenging topic in electronic circuit design. Methods for yield optimization based on Monte Carlo (MC) analysis of a circuit whose behavior is reproduced by simulations usually require too many time expensive simulations to be effective for iterative optimization. In this paper, we propose a method which tackles the yield optimization problem by combining a support vector machine (SVM) surrogate model (SM) of the circuit to perform the MC analysis and evaluate the yield, and an efficient optimization method to maximize the yield evaluated using the SVM SM. We report the numerical results obtained for the design of two real consumer circuits provided by STMicroelectronics, and we compare these results with the ones obtained using the industrial benchmark currently adopted at STMicroelectronics for yield optimization. These preliminary results show that the method is promising to be very efficient and capable of reaching design solutions with high values of the yield. [ABSTRACT FROM PUBLISHER]

This paper proposes a technique, GALAXY, to speed up multicircuit simulation, where each circuit under simulation is identical in schematic but different in some parameters. GALAXY is based on the successive chord method, where the inverse Jacobian matrix ( J ^-1 ) is reused to simulate many circuits whose solutions are similar. GALAXY also speeds up single-circuit simulation by reusing J ^-1 between consecutive time steps. Compared with a traditional Newton–Raphson (NR) simulator, on average, GALAXY reduces runtime of single-circuit and multicircuit simulation by 44% and 71%, without loss of accuracy. The number of NR iterations is reduced by 78%. [ABSTRACT FROM PUBLISHER]

Given a chip that produced a faulty output response to a test set, a defect diagnosis procedure produces a set of candidate faults that is expected to identify the defects that are present in the chip. The accuracy of the set of candidate faults is higher when the set is smaller or when its overlap with the defects that are present in the chip is larger. To increase the accuracy of a set of candidate faults, this paper describes an approach where several sets of candidate faults are computed based on different subsets of the test set. The subsets are obtained by removing small numbers of tests from the complete test set. The result is sets of candidate faults that are similar but not identical. The number of sets where a fault appears yields a confidence level that the fault actually belongs in a set of candidate faults. New sets of candidate faults are defined based on the confidence levels obtained. The smallest set of candidate faults can be used as the final result of defect diagnosis, or the sets can be used for ranking the candidates. Experimental results for benchmark circuits demonstrate the effectiveness of this approach. [ABSTRACT FROM PUBLISHER]

Test generation for hard-to-reach states is important in functional verification. In this paper, we present a path constraint solving-based test generation method (PACOST) which operates in an abstraction-guided semiformal verification framework to cover hard-to-reach states. PACOST combines concrete simulation and symbolic simulation on the design under verification for path constraint extraction and mutation, and uses a sequential path constraint extractor to generate a set of valid input vectors for exploring different simulation paths with different next states. It then works on a target state-oriented abstract model to select the next state with the smallest abstract distance. In addition, the value of register variables in control logic can be controlled by analyzing the data dependence between variables, which helps the simulation converge to the target states. Experimental results show that PACOST can generate shorter traces reaching hard-to-reach states, in comparison with previous abstraction-guided semiformal methods. [ABSTRACT FROM AUTHOR]

Real-time simulation of induction machine plays a crucial role in hardware-in-the-loop (HIL) scenarios. Due to the key advantages offered by magnetic equivalent circuits (MEC) for modeling induction machines compared with finite element analysis and electric equivalent circuits in terms of computational expense and achieved accuracy, this paper proposes a real-time nonlinear MEC of the induction machine. The model is emulated in real time on the field-programmable gate array (FPGA) by exploiting the parallel hardware architecture and fully pipelined arithmetic processing. The performance of the FPGA-based real-time emulated induction machine model is investigated and compared with the behavior of an experimental setup of induction machine and finite element results to demonstrate the effectiveness and accuracy of proposed approach for HIL applications. [ABSTRACT FROM PUBLISHER]

In this paper, a novel methodology for high-level modeling of bus communication in embedded systems is introduced. It allows the dynamic evaluation of their signal integrity (SI) characteristics at the virtual prototyping step (i.e., before physical realization). The method is based on the association of functional and nonfunctional modules. Functional modules represent the ideal behavior of the system, while nonfunctional modules use neural networks to model SI effects. This approach was implemented in SystemC-AMS, using the timed data flow model of computation. The method is illustrated by a Universal Serial Bus (USB) 3.0 application, where modular and parameterizable models are introduced. The method achieved good accuracy (<5%) while allowing significant simulation speedup (up to 2000 times), compared with SPICE-based reference models. This methodology can be used to perform an early SI analysis in the virtual prototyping of bus communication in the embedded systems. [ABSTRACT FROM PUBLISHER]

In this paper, a robust model-based battery state-of-charge (SOC) estimating algorithm is proposed with a novel approach based on combination of multimodels data-fusion technique and particle filter (PF). The proposed method is particularly adapted for SOC estimation under real-time conditions and the presence of measurement noise. In this innovative approach, multiple battery models have been used in order to accurately estimate a battery SOC. During the estimation process, the measured battery terminal voltage is compared with the multiple battery models output to generate individual residual, which is then used to calculate the weight of estimated value from each battery model. This weight, which represents the accuracy of observation equation of each battery model, is inversely proportional to the residual. The estimated SOC values from different models are then fused and the weights of estimated values from each battery model are adjusted dynamically using PF and weighted average methodology, in order to calculate the final SOC estimation of the battery. For each proposed battery model, the corresponding parameter-tuning strategies are also presented. In addition, the proposed method has been validated by experimental results. The results demonstrate that the proposed multimodels-based algorithm can be implemented effectively for real-time application, and achieve better accuracy than single model-based methods. [ABSTRACT FROM AUTHOR]

Lithium (Li)-ion battery cells suffer from significant performance degradation at subzero temperatures. This paper presents a predictive control-based technique that exploits the increased internal resistance of Li-ion cells at subzero temperatures to increase the cell’s temperature until the desired power can be delivered. Specifically, the magnitude of a sequence of bidirectional currents is optimized such as to minimize total energy discharged. The magnitude of current is determined by solving an optimization problem that satisfies the battery manufacturer’s voltage and current constraints. Drawing bidirectional currents necessitates that a temporary energy reservoir for energy shuttling, such as an ultracapacitor or another battery, be available. When compared with the case when no penalty on energy withdrawn is imposed, simulations indicate that reductions of up to 20% in energy dispensed as heat in the battery as well as in the size of external storage elements can be achieved at the expense of longer warm-up operation time. [ABSTRACT FROM PUBLISHER]

This paper investigates the ways to detect defects in photovoltaic (PV) cells and panels. Here, two different methods have been used. First, the output behavior was characterized by measuring the amount of current at different voltage levels to obtain the current–voltage and power–voltage curves. Second, infrared emissions of forward-biased nonilluminated PV cells and panels were measured by the use of synchronized thermography. From these measurements, temperature maps can be derived, which indicate that the temperature within a given PV cell unevenly rises due to the defects in the cell. Uneven temperature distribution indicates defects and reduced output power. [ABSTRACT FROM AUTHOR]

This paper proposes a wideband scalable circuit model for tapered through-package vias (TPVs) in glass interposers. By slicing TPVs horizontally into infinitesimally thin pieces and integrating along TPVs, an analytical solution was derived for the parasitic resistance ( $R$ ), while semianalytical expressions were derived for the parasitic inductance ( L$ ), capacitance ( C$ ), and conductance ( G magnitude and S_{21} phases being less than 0.01 dB and 1°, respectively. In addition, two dual-via chains of different lengths were designed, fabricated, and measured to benchmark the proposed model up to 20 GHz. The excellent consistency between them further proves the validity of the proposed model. Finally, the effect of the TPV taper was comprehensively studied on the RLCG parameters. It was found that the TPV taper was beneficial to reduce the parasitic capacitance and conductance by as much as 40%. Despite these benefits, tapered TPVs are not preferred, because the parasitic resistance and inductance are the dominant factors for TPVs in glass, and the TPV taper increases the parasitic resistance drastically and also increases the parasitic inductance by as much as 80%. [ABSTRACT FROM AUTHOR]

This paper presents a solution strategy for planning and project distribution system problems. This model applies concepts of Tabu Search (TS) metaheuristic to provide a complete solution for the problem, from distribution substations to individual consumers, making it able to be implemented by distribution companies. A 50-bus network was used to evaluate this method that obtained feasible and good solutions for planning and project distribution systems. [ABSTRACT FROM PUBLISHER]

This paper presents a control system methodology based on system identification (SI) to derive state matrices and system dynamics for the extrapolation of simulated time-domain electromagnetic (EM) responses using both input and output data. The method is applied to model transient responses for a dielectric resonator and a wideband slot antenna computed by the finite-integration method using non-Gaussian excitation pulses typically employed in digital signals. Using state-space SI formulation, a compact representation of the output time-domain signal is derived, including the early-time transient responses, and its numerical implementation depicts no instability in late-time responses plotted well beyond the steady state. Furthermore, all the system poles are found to lie within the unit circle in the complex plane. Excellent model corroboration is achieved with independently computed frequency domain data or measured results using modest computer resources. [ABSTRACT FROM AUTHOR]

This paper deals with a new method of metamodel construction for electromagnetic compatibility (EMC) simulation of power electronic converters. The proposed method uses a compressed wavelet coefficients vector of a time-domain signal and a learning method [support vector regression (SVR)]. This can be applied for a black box approach of modeling of complex systems such as power converters. This allows the study of EMC behavior, the impact of the uncertainties and their propagations inside the model or the design of EMC filters. [ABSTRACT FROM PUBLISHER]

This paper stresses the importance of applying circuit theory in circuit simulation. Circuit simulation is a combination of circuit theory and numerical analysis. Both the theoretical basis and the numerical algorithms should be robust and accurate to produce reliable and correct results. This communication focuses on the theoretical and practical aspects of circuit equation formulation in the simulation of circuits containing nanodevices. [ABSTRACT FROM PUBLISHER]

Due to the inconsistent and varied characteristics of lithium-ion battery (LiB) cells, battery pack modeling remains a challenging problem. To model the operation of each cell in the battery pack, considerable work effort and computation time are needed. This paper proposes a data-driven bias-correction-based LiB modeling method, which can significantly reduce the computation work and remain good model accuracy. [ABSTRACT FROM AUTHOR]

Supercapacitors benefit from unique features including high power density, long cycle life, wide temperature operation range, durability in harsh environments, efficient cycling, and low maintenance cost. This paper presents a validated lumped and computationally efficient electrical and thermal model for a cylindrical supercapacitor cell. The electrical model is a two-state equivalent electric circuit model with three parameters that are identified using temporal experiments. The dependence of the parameters on the state of charge, current direction and magnitude (20–200 A), and temperatures ranging from -40 °C to 60 °C is incorporated in the model. The thermal model is a linear 1-D model with two states. The reversible heat generation which is significant in double-layer capacitors is included in the thermal model. The coupling of the two models enables tuning of the temperature-dependent parameters of the electrical model in real time. The coupled electrothermal model is validated using real-world duty cycles at subzero and room temperatures with root-mean-square errors of (82 mV–87 mV) and (0.17 °C–0.21 °C) for terminal voltage and temperature, respectively. This accurate model is implementable in real-time power applications and also thermal management studies of supercapacitor packs. [ABSTRACT FROM PUBLISHER]

To study a multirate system, each subsystem can be solved by a dedicated software with respect to the physical problem and the time constant. Then, the problem is the coupling of the solutions of the subsystems. The waveform relaxation method (WRM) seems to be an interesting solution for the coupling, but until now, it has been mainly applied on academic examples. In this paper, the WRM is applied to perform the coupling of a controlled rectifier and a non-linear finite element model of a transformer. [ABSTRACT FROM AUTHOR]

Among the model order reduction techniques, the proper generalized decomposition (PGD) has shown its efficiency to solve static and quasistatic problems in the time domain. However, the introduction of non-linearity due to ferromagnetic materials, for example, has never been addressed. In this paper, the PGD technique combined with the discrete empirical interpolation method (DEIM) is applied to solve a non-linear magnetostatic problem coupled with the circuit equations. To evaluate the reduction technique, the transient state of a three-phase transformer at no load is studied using the full finite-element model and the PGD–DEIM model. [ABSTRACT FROM AUTHOR]

As a portable high-performance computing technology for electromagnetic wave simulations, several kinds of dedicated computers for the finite-difference time-domain (FDTD) method have been considered. We previously proposed a dataflow architecture FDTD dedicated computer and showed that the estimated performance of the FDTD dataflow machine could exceed those of the high-end PC and GPU computers. On the other hand, the digital circuit of our previously proposed FDTD dataflow machine was inefficiently implemented in the field-programmable gate array (FPGA) owing to dual-mode operations of the normal grids and the perfectly matched layer (PML) grids, that is, almost half parts of the FPGA hardware resources were not used in our previously proposed machine. This paper proposes a modified architecture of the 3-D FDTD dedicated computer to improve the inefficient use of the FPGA hardware resources. The modified digital circuit of the FDTD scheme is designed to execute the FDTD calculation for eight normal grids or four PML grids. In the modified machine, there are almost no unused parts of hardware resources, and double size of FDTD scheme circuits can be implemented in the same size FPGA compared with the previously proposed machine. [ABSTRACT FROM AUTHOR]

This paper presents the generation of equivalent circuits from a finite-element (FE) model of electromagnetic devices using proper orthogonal decomposition (POD). This method effectively computes the frequency response of the reduced FE model constructed by the POD-based model order reduction. Then, the circuit parameters are determined so as to minimize the error between the frequency responses of the reduced FE model and equivalent circuit. The frequency characteristics of an inductor and the induction heating machine evaluated by the equivalent circuit are shown to be in good agreement with those computed from the original FE model. [ABSTRACT FROM AUTHOR]

This paper proposes an equivalent-circuit generation from the finite-element (FE) model of electromagnetic devices using a model order reduction (MOR). In this method, an equivalent circuit is directly generated from the reduced transfer function obtained using MOR based on Padé approximation via the Lanczos process. It is shown that the generated circuit yields sufficiently accurate results in both frequency and time domains. Moreover, the computational time of the present method is much shorter than that of the circuit generation based on frequency sweep using the conventional FE analysis. [ABSTRACT FROM AUTHOR]

In this paper, we propose SVR-NoC, a network-on-chip (NoC) latency model using support vector regression (SVR). More specifically, based on the application communication information and the NoC routing algorithm, the channel and source queue waiting times are first estimated using an analytical queuing model with two equivalent queues. To improve the prediction accuracy, the queuing theory-based delay estimations are included as features in the learning process. We then propose a learning framework that relies on SVR to collect training data and predict the traffic flow latency. The proposed learning methods can be used to analyze various traffic scenarios for the target NoC platform. Experimental results on both synthetic and real-application traffic demonstrate on average less than 12% prediction error in network saturation load, as well as more than $100\times $ speedup compared to cycle-accurate simulations can be achieved. [ABSTRACT FROM PUBLISHER]

Traditionally, model order reduction methods have been used to reduce the computational complexity of mathematical models of dynamic systems, while preserving their functional characteristics. This technique can also be used to fasten analog circuit simulations without sacrificing their highly nonlinear behavior. In this paper, we present an iterative approach for reducing the computational complexity of nonlinear analog circuits using piecewise linear approximations, $k$ -means clustering, and Krylov space projection techniques. We model primary circuit inputs, design initial conditions, and circuit parameters as fuzzy variables with different distributions in qualitative simulations. We then iteratively fine-tune the reduced models until a model is achieved that meets a predefined performance and accuracy conformance criteria. We demonstrate the effectiveness of our method using several key nonlinear circuits: 1) a transmission line; 2) a ring oscillator; 3) a voltage controlled oscillator; 4) a phase-locked loop; and 5) an analog comparator circuit. Our experiments show that the reduced model simulations are fast and accurate compared with the existing techniques. [ABSTRACT FROM PUBLISHER]

A detailed power transformer electromagnetic transient model would help in accurately predicting transient stresses and formulating adequate protection strategies in power systems. This paper presents a real-time nonlinear high-resolution magnetic equivalent circuit (HR-MEC) based transformer model on the field-programmable gate array for hardware-in-the-loop simulation. This model is inspired by the mesh generated in finite-element method (FEM) tools to depict the major flux paths in the transformer. All of the major nonlinear phenomena such as saturation, hysteresis, and eddy currents are captured in the transformer hardware emulation whose modules were developed in a 32-b floating point precision VHDL. The developed HR-MEC model and nonlinear numerical solution have been fully parallelized in hardware to achieve the lowest latency in the real-time implementation. The hysteresis in the transformer core is modeled using Preisach theory, and eddy currents are incorporated using a frequency-dependent network. The real-time results are validated using 3-D FEM analysis in JMAG software. [ABSTRACT FROM PUBLISHER]

A compact model for the single-poly multitime programmable (MTP) memory cells is presented in this paper for the first time. It is based on the charge balance approach, while the traditional old model is on the fixed capacitive coupling approach. The proposed cell model has been implemented by Verilog-A and integrated into commercial SPICE simulator. The model supports both dc and transient analyses, and the simulated results are consistent very well with those from device simulation and measurement, whereas the results by the traditional old model deviate substantially. Furthermore, the comprehensive optimization of the MTP cells is made feasible thanks to the new model, such as device size, high voltage ramp rate, and reliability prediction. As a result, this compact cell model will be very useful for the designers to evaluate and optimize a single-poly MTP cell. [ABSTRACT FROM AUTHOR]

Power system transient analysis relies on the deployment of models with ever-increasing accuracy that represents the system's frequency-dependent components with respect to the phenomena being scrutinized. A key issue in this context is the construction of a model yielding passive properties for each system component. Such properties are commonly compromised by corrupting noise in measurements that serve as input to the computation of blackbox models. In addition, model passivity could be further compromised during parameter estimation. This paper undertakes the task of developing a proposal to build an optimization methodology based on linear matrix inequalities (LMI-based) which is intended for obtaining an optimal, passive, blackbox model for a n-terminal power transformer. The resulting model can be further realized as a circuit representation in order to simulate the transformer dynamics in an Eletromagnetic Transient program (EMT type). The results derived from two operating power transformers are later provided to confirm how effective the procedure herein proposed is. [ABSTRACT FROM PUBLISHER]

In this paper, a new collaborative tracking algorithm is put forward to track multiple objects in video streams. First, we suggest a robust color-based tracker whose model is updated by online learned contextual information. A recursive method is performed to improve the estimation accuracy and the robustness to cluttered environment. Then, we extend this tracker to multiple targets. To avoid the problem of id-switch in long-term occlusion, we design a hierarchical tracking system with different tracking priorities. First, the algorithm employs an adaptive collision prevention model to separate the nearby trajectories. When the inter-occlusion happens, the holistic model of tracker splits into several parts, and we use the visible parts to perform tracking as well as occlusion reasoning. In the case where the targets have close appearance models, a trajectory monitoring approach is employed to handle the occlusion. Once the tracker is fully occluded, the algorithm will reinitialize particles around the occluder to capture the reappeared target. Experimental results using open dataset demonstrate the feasibility of our proposal. In addition, comparison with several state-of-the-art trackers has also been performed. [ABSTRACT FROM PUBLISHER]

In this paper, we propose a chip-scale Chemical mechanical polishing (CMP) model based on the Greenwood–Williamson theory combining the effects of both the pad bulk deformation and the feature size, which are mainly responsible for global pressure distribution and feature-scale removal rate variation, respectively. A reference camber is first constructed to simulate the pad bulk deformation, which can be directly introduced into the global pressure distribution computation for incorporating the long-range characteristics of chip profiles. Then, both the effective curvature and the modified distribution function of pad asperity height are involved in the material removal rate. The model is first verified through some experimental data from CMP test structures and found to be in good agreement with the test data. For further validating the rationality and accuracy of the present model, some simulations are compared with our experimental data and discussed in detail. [ABSTRACT FROM PUBLISHER]

This paper introduces physics-based stripline ports for a segmented optimization of component footprints on printed circuit boards (PCBs). A segmentation is used for dividing a digital communication system into well-defined parts that are considered to be mostly independent. This technique is widely used in conjunction with generic 3-D electromagnetic field solvers, but it is new to physics-based models that until now only allow for ports at the upper and lower via ends, i.e., on PCB surfaces. Evidence of feasibility is provided by means of correlation with measurements and full-wave simulations up to 40 GHz. Since physics-based models can efficiently capture and simulate even systems of thousands of elements within acceptable computation time, the results of a segmented simulation can easily be compared to the full-board environment. The corresponding results are correlated to investigate limitations. [ABSTRACT FROM AUTHOR]

This paper presents an accurate analytical compact model for Schottky-barrier-type graphene nanoribbon field-effect transistors (SB-GNRFETs). This is a physics-based analytical model for the current–voltage ( $I$ – $V$ ) characteristics of SB-GNRFETs. The proposed model considers various design parameters and process variation effects, including graphene-specific line-edge roughness, which allows thorough exploration and evaluation of SB-GNRFET circuits. We develop accurate approximations of SB tunneling, channel charge, and current, which provide accurate results while maintaining model compactness. We evaluate the effect of design parameters and process variations on the performance of SB-GNRFETs. We also compare circuit-level performance of SB-GNRFETs with multigate (MG) Si-CMOS (e.g., FinFETs). Our circuit simulations indicate that SB-GNRFET has an energy-delay product (EDP) advantage over Si-CMOS, although GNR-specific process variation, especially the line-edge roughness, would significantly downgrade such an advantage; the EDP of the ideal SB-GNRFET (assuming no process variation) is $\sim 2.5$ % of that of Si-CMOS, while the EDP of the nonideal case with process variation is $\sim 68$ % of that of Si-CMOS. Finally, we study technology scaling with SB-GNRFET and MG Si-CMOS. We show that the EDP of ideal (nonideal) SB-GNRFET is $\sim 0.88$ % (54%) EDP of that of Si-CMOS as the technology nodes scale down to 7 nm. [ABSTRACT FROM AUTHOR]

The aim of this paper is to present a six-phase induction machine (6PIM) model based on the so-called circuit-oriented approach suitable for simulation of electrical faults on both stator and rotor sides. This specific model has been developed by using only resistances, inductances, and controlled voltage sources. The coupling effects between both the stator and the rotor have been taken into account by the computation of stator–rotor mutual inductances. The model has been developed under the MATLAB/Simulink environment in order to have a universal tool that is easy to use with any control techniques. With this model, it is possible to simulate any type of electrical faults during the motion by closing or opening corresponding switches. The performances of the model have been validated by comparing simulation and experimental results of a 90-W 14-V 50-Hz two-pole 6PIM operating with different levels of load torque in healthy and faulty modes. Furthermore, this model has been associated to a fault-tolerant speed control method in phase opening occurrences in order to test the model accuracy. [ABSTRACT FROM AUTHOR]

Compact modeling of phase-locked loop (PLL) frequency synthesizer is proposed to reduce transient phase noise and jitter simulation time. Conventional small-signal noise assumption based frequency-domain simulation approach produces inaccurate results for nonlinear PLLs. Accurate analysis of nonlinear PLL are possible through time-domain, or transient noise simulation but time-domain simulation is computation-intensive and time-consuming. This paper presents a practical solution for transient phase noise and jitter analysis using compact modeling techniques. It features an autoregressive moving average process modeled voltage-controlled oscillator with fractional calculus and wavelet transform for phase noise decomposition and reconstruction, thereby reducing the phase noise and jitter simulation time to 25.8% of the transistor-level simulation with 0.4 dB @ 1 MHz phase noise error and 0.3 ps long-term jitter error for a 2 GHz PLL frequency synthesizer in a 65 nm CMOS process. [ABSTRACT FROM PUBLISHER]

Piezoelectric actuators (PEAs) have been widely used in nanotechnology due to their characteristics of fast response, large mass ratio, and high stiffness. However, hysteresis, which is an inherent nonlinear property of PEAs, greatly deteriorates the control performance of PEAs. In this paper, a nonlinear model predictive control (NMPC) approach is proposed for the displacement tracking problem of PEAs. First, a “nonlinear autoregressive–moving-average with exogenous inputs” (NARMAX) model of PEAs is implemented by multilayer neural networks; second, the tracking control problem is converted into an optimization problem by the principle of NMPC, and then, it is solved by the Levenberg–Marquardt algorithm. The most distinguished feature of the proposed approach is that the inversion model of hysteresis is no longer a necessity, which avoids the inversion imprecision problem encountered in the widely used inversion-based control algorithms. To verify the effectiveness of the proposed modeling and control methods, experiments are made on a commercial PEA product (P-753.1CD, Physik Instrumente), and comparisons with some existing controllers and a commercial proportional–integral–derivative controller are conducted. Experimental results show that the proposed scheme has satisfactory modeling and control performance. [ABSTRACT FROM PUBLISHER]

Unknown (X) values emerge during the design process as well as during system operation and test application. X-sources are for instance black boxes in design models, clock-domain boundaries, analog-to-digital converters, or uncontrolled or uninitialized sequential elements. To compute a test pattern for a given fault, well-defined logic values are required both for fault activation and propagation to observing outputs. In presence of X-values, conventional test generation algorithms, based on structural algorithms, Boolean satisfiability (SAT), or binary decision diagram-based reasoning may fail to generate test patterns or to prove faults untestable. This paper proposes the first efficient stuck-at and transition-delay fault test generation algorithm able to prove testability or untestability of faults in presence of X-values. It overcomes the principal pessimism of conventional algorithms when X-values are considered by mapping the test generation problem to the SAT of quantified Boolean formulas. Experiments on ISCAS benchmarks and larger industrial circuits investigate the increase in fault coverage for conventional deterministic and potential detection requirements for both randomized and clustered X-sources. [ABSTRACT FROM PUBLISHER]

In this paper, the problem of geometry scaling of compact microwave structures is investigated. As opposed to conventional structures [i.e., constructed using uniform transmission lines (TLs)], re-design of miniaturized circuits (e.g., implemented with artificial TLs) for different operating frequencies is far from being straightforward due to considerable cross-couplings between the circuit components. Here, we develop a simple and computationally efficient methodology for dimension scaling of the compact circuits. The proposed approach utilizes an equivalent circuit representation to identify a fast inverse model that determines the relationship between the geometry parameters of the structure at hand and its operating frequency. Upon suitable correction, the inverse model is applied to find dimensions of the scaled design at the high-fidelity (electromagnetic (EM) simulation) model level. Owing to reasonable correlations between the low- and high-fidelity models, the circuit geometry scaled to a requested operating frequency can be found using just a single EM simulation of the structure, despite possible absolute discrepancies between the models. The proposed methodology is demonstrated using two exemplary compact couplers scaled in wide ranges from 0.5 to 2 GHz and from 0.5 to 1.8 GHz, respectively. The numerical results are supported by physical measurements of the fabricated coupler prototypes. [ABSTRACT FROM PUBLISHER]

In this paper, a new practical method is presented to estimate supercapacitor state for wireless sensor nodes. The self-discharge process of supercapacitor, as an energy storage device in sensor nodes, is usually considered as the main factor that needs to be taken into account for power management. Recent studies have demonstrated that a supercapacitor charge-redistribution process may also have significant impact on power management. To consider charge redistribution in power management of a real-time system, a practical method is presented to estimate the state of a supercapacitor. The accuracy of the method is validated by experiments. The impact of time step on the proposed model is also investigated. The results indicate that the proposed model can achieve good accuracy with relatively large time step. Moreover, the model is easy to implement, and has low memory usage and computational cost for practical applications in a real-time system. Based on the practical model, estimations of charge and energy transferred during the redistribution process are presented, which provide important information toward developing energy aware algorithms in wireless sensor networks. [ABSTRACT FROM AUTHOR]

This paper presents a generic hybrid optimization methodology based on space mapping techniques for the design of various high voltage pulse transformer structures used in klystron modulators. It is using two dimensioning models with different levels of complexity: a coarse model based on 2D FEA less accurate but cheaper to evaluate and a fine 3D FEA model more accurate but time consuming. A specific correction mechanism is applied to align the 2D FEA dimensioning model with the more accurate 3D FEA dimensioning model. With a suitable selection of the correction factors, the convergence of this hybrid optimal design methodology is obtained with a limited number of time consuming 3D FEA simulations. The method is applied to the optimal design of a monolithic high voltage pulse transformer for the CLIC klystron modulator. The influence of the klystron operating voltage on the size of the optimal pulse transformer is evaluated with the proposed design methodology. [ABSTRACT FROM AUTHOR]

This paper investigates the impact of cell variability on the read performance of the one-selector one-resistor (1S1R) cross-point array. A variability-aware array-sizing analysis methodology is introduced, considering three independent variability sources, namely, the data pattern randomness, the selector variability, and the resistive switching element (RSE) variability. By analyzing the impact of each variability factor separately, we show that the data pattern randomness is not an important contributor for the read margin (RM) degradation. While the intrinsic RSE variability reflected in the narrowing of the ON/OFF RSE window degrades the RM, the selector variability adds to this further, mainly affecting the ON-state readout current, and causing extra RM degradation. To accommodate cell variability and guarantee acceptable read performance, additional cell performance margin is required. The 1S1R requirements are extrapolated for 1-Mb array, assuming variability-affected cells. It is found that, with a typical selector variability, a minimal RSE window of 5 and a selector half-bias nonlinearity of $\sim 8000$ are required to achieve at least 10% RM. [ABSTRACT FROM AUTHOR]

Superparamagnetic tunnel junctions (SMTJs) are noise powered stochastic oscillators, which can harness thermal energy through phenomena such as stochastic resonance and noise-induced synchronization. This enables them to operate with the minimal externally supplied energy, and therefore, makes them promising candidates for implementing bioinspired computing schemes. These applications require understanding how SMTJs can be integrated into CMOS circuits. In this paper, we present a compact model of SMTJ, written in the VerilogA language, that can be used within standard integrated circuit design tools. This compact model is based on the Néel–Brown model and allows for fast simulations. We show that this model can reproduce the experimental characterization of a sample subjected to different values of dc currents. Then, we definitively demonstrate the validity of the model by confronting it to the experimental results in the case of a complex phenomenon: noise-induced synchronization. [ABSTRACT FROM AUTHOR]

Multicore instruction-set simulation (MCISS) has become more and more important due to tremendous increase in number of multicore designs. To boost the speed of MCISS, one of the most effective and commonly used approaches is parallel simulation. However, timing synchronization must be applied to ensure accurate simulation results of parallel MCISS, and may induce huge synchronization overhead. In this paper, we propose a highly efficient and effective parallel MCISS approach by synchronizing timing before each synchronization function (SF) call. We improve the applicability of the state-of-the-art critical-section-level simulation approach with a generic blocking/nonblocking send/receive model covering all types of SFs. To further reduce synchronization overhead, we also introduce optimization methods such as a hybrid scheduling technique and provide an analysis algorithm that helps the designers to choose the host platform with the best simulation performance. Experiments show that the proposed approach attains a simulation speed of up to 285 MIPS, while producing accurate timing and functional results. [ABSTRACT FROM AUTHOR]

In this paper, an adjoint state-space dynamic neural network method for modeling nonlinear circuits and components is presented. This method is used for modeling the transient behavior of the nonlinear electronic and photonic components. The proposed technique is an extension of the existing state-space dynamic neural network (SSDNN) technique. The new method simultaneously adds the derivative information to the training patterns of nonlinear components, allowing the training to be done with less data without sacrificing model accuracy, and, consequently, makes training faster and more efficient. In addition, this method has been formulated such that it can be suitable for the parallel computation. The use of derivative information and parallelization makes training using the proposed technique much faster than the SSDNN. In addition, the models created using the proposed method are much faster to evaluate compared with the conventional models present in traditional circuit simulation tools. The validity of the proposed technique is demonstrated through the transient modeling of the physics-based CMOS driver, commercial NXP’s 74LVC04A inverting buffer, and nonlinear photonic components. [ABSTRACT FROM PUBLISHER]

Emerging nonvolatile universal memory technology is vital for providing the huge storage capabilities, which is needed for nanocomputing facilities. Memristor, which is recently discovered and known as the missing fourth circuit element, is a potential candidate for the next-generation memory. Memristor has received extra attention in the last few years. To support this effort, this paper presents a novel read/write circuit that facilitates the reading and writing operation of the Memristor device as a memory element. The advantages of the proposed read/write circuit are threefold. First, the proposed circuit has a nondestructive successive reading cycle capability. Second, it occupies less die area. Finally, the proposed read/write circuit offers a significant improvement in power consumption and delay time compared with other read/write circuits. [ABSTRACT FROM PUBLISHER]

Commercial photovoltaic (PV) modules are made of different PV cell technologies such as monocrystalline, multicrystalline, amorphous silicon, and copper indium diselenide. Usually, a single- or a double-diode PV model is used to model the output characteristic. However, it is unclear which PV model is optimal for each PV cell technology as the modeling accuracy is dependent on the PV model used. To fill up this research gap, a generalized multidimension $(n \times m)$ diode PV model is proposed in this paper to determine the optimal PV model. The proposed PV model allows the diode network to be configured to better fit the output characteristics of different PV cell technologies. Both simulation and experimental results are presented to illustrate the advantages of the proposed model. From the results, the optimal PV model that matches each of the cell technology is established. They can be used as a reference PV model for future works. [ABSTRACT FROM PUBLISHER]

This paper presents a general method for building equivalent electric circuits of power transformers, including eddy current effects in windings and core. A high-frequency equivalent dual model for single- and three-phase transformers with two multilayer windings is derived from the application of the principle of duality. The model is built from elements available in circuit simulation programs, such as Electromagnetic Transients Program (EMTP)–Alternative Transients Program, EMTP-RV, PSCAD, and PSpice. The parameters of the frequency-dependent leakage inductance and winding resistance are computed with analytical formulae obtained from the solution of Maxwell’s equations that are based on the geometrical dimensions and material information. Ideal transformers are utilized to isolate the electric components (winding resistors and capacitors) from the magnetic components (inductors). The physically correct connection points for electric and magnetic components are clearly identified. The proposed methodology is successfully validated versus finite- element simulations and laboratory measurements. [ABSTRACT FROM PUBLISHER]

To improve the efficiency of direct solution methods in SPICE-accurate integrated circuit (IC) simulations, preconditioned iterative solution techniques have been widely studied in the past decades. However, it is still an extremely challenging task to develop robust yet efficient general-purpose preconditioning methods that can deal with various types of large-scale IC problems. In this paper, based on recent graph sparsification research we propose circuit-oriented general-purpose support-circuit preconditioning (GPSCP) methods to dramatically improve the sparse matrix solution time and reduce the memory cost during SPICE-accurate IC simulations. By sparsifying the Laplacian matrix extracted from the original circuit network using graph sparsification techniques, general-purpose support circuits can be efficiently leveraged as preconditioners for solving large Jacobian matrices through Krylov-subspace iterations. Additionally, a performance model-guided graph sparsification framework is proposed to help automatically build nearly-optimal GPSCP solvers. Our experiment results for a variety of large-scale IC designs show that the proposed preconditioning techniques can achieve up to 18 \times runtime speedups and 7 \times memory reduction in DC and transient simulations when compared to state-of-the-art direct solution methods. [ABSTRACT FROM PUBLISHER]

With the steady growth of chip complexity and shrinking feature size, multiple challenges are emerging for transistor level circuit simulation. Compact SPICE models are a fundamental part of circuit verification, serving as a bridge between the semiconductor design and foundry. It is also an integral part of SPICE simulators, which directly affects tool performance and therefore design schedule. While the advanced 3-D technology nodes deliver superior level of scalability, simulation cost is rapidly increasing due to the computational complexity introduced by device model equations and the number of iterations required for numerical methods. In this paper, an efficient solution is proposed to reduce the computational cost associated with UC Berkeley BSIM-CMG device model evaluation, by applying robust Verilog compiler and computer algebra techniques to the device model equations. As a result of this implementation, simulation time reduction is up to 72% for complex blocks of the latest generation processor design. [ABSTRACT FROM PUBLISHER]

This paper proposes a numerical solution of the nonlinear equations that describes the hysteretic behavior of ferromagnetic materials. From the proper definition and solution of these equations, an equivalent circuit model for a ferromagnetic core is developed and proposed. The results obtained from the equivalent circuit are compared with those obtained by a rigorous numerical solution. [ABSTRACT FROM AUTHOR]