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Based on the IEEE 802.16e standard's (672,336) LDPC code and the normalized Min-Sum decoding algorithm, this paper designs and implements an LDPC decoder that optimizes the channel information. The correction factor for check nodes is converted into a correction factor for the initial channel information, replacing the optimization of check node information with that of initial channel information. This achieves decoding performance equivalent to the traditional normalized Min-Sum decoding algorithm. Different correction factor values vary in complexity during FPGA implementation, as they involve different amounts of shift-add operations. For NMS decoding requiring a high number of shift-add operations to achieve optimal correction values, this can be converted into an LDPC decoding algorithm optimized for channel information, reducing computational overhead without sacrificing performance. A partially parallel improved decoder was designed and implemented on an FPGA, and its feasibility was verified using the Vivado simulation platform. [ABSTRACT FROM AUTHOR]

This study investigates receiver design solutions for distributed Massive Multiple Input Multiple Output (D-m MIMO) systems, taking into account parameters such as number of access points as well as concerns related to channel estimates that use single-carrier frequency-domain equalization (SC-FDE). A significant contribution of this research is the integration of Low-Density Parity-Check (LDPC) codes to simplify coding complexity and enhance communication efficiency. The research examines different receiver designs, such as spatial antenna correlation and sophisticated channel estimation methods. The authors propose integrating LDPC codes into the receiver architecture to simplify computations and enhance error correction and decoding. Moreover, the paper examines performance evaluation measures and approaches, highlighting the trade-offs among complexity, spectral efficiency, and error performance. The comparative analysis indicates the benefits, in terms of performance, of incorporating LDPC codes and improving system throughput and dependability. We examine four distinct receiver algorithms: zero-forcing (ZF), minimum mean square error (MMSE), maximum ratio combining (MRC), and equal gain combining (EGC). The study shows that MRC and EGC receivers work well in D-m MIMO because they make the receiver system less computationally demanding. [ABSTRACT FROM AUTHOR]

A new decoding method for low-density parity-check (LDPC) codes is presented to lower the energy consumption of LDPC decoders for NAND flash-based storage systems. Since the channel condition of NAND flash memory is reliable for most of its lifetime, it is inefficient to apply the maximum-effort decoding with the full parity-check matrix (H-matrix) from the beginning of the lifespan. As the energy consumption and the decoding latency are proportional to the size of the H-matrix used in decoding, the proposed algorithm starts the decoding with a partial H-matrix selected by considering the channel condition. In addition, the proposed partial decoding provides various error-correcting capabilities by adjusting the partial H-matrix. Based on the proposed partial decoding algorithm, a prototype decoder is implemented in a 65 nm CMOS process to decode a 4 KB LDPC code. The proposed decoder reduces energy consumption by 93% compared to the conventional LDPC decoding architecture at maximum. [ABSTRACT FROM AUTHOR]

Satellite communications face difficulties such as intensified environmental attenuation, dynamic time-varying links, and diverse business scenarios, which usually require channel coding schemes with high coding gain and high throughput. Low-density parity-check (LDPC) codes are dominant in satellite communication coding schemes due to their excellent performance in approaching the Shannon limit and the characteristics of parallel computing. The traditional weighted-Algorithm B decoding algorithm ignores the channel received information and involves frequent multiplication operations and iteration, which introduces the channel received information for hard-decision and constellation mapping processing. Meanwhile, we design the correlated reliability between the extrinsic information and the mapping processing information to improve the correctness of decoding. The multiplication operation in the iterative process can be replaced by the simple sum of the Hamming distance coefficient, the correlated reliability between the extrinsic information and the mapping processing information, and the extrinsic information frequency, thereby reducing the complexity and storage load of the system. The simulation results show that the presented MRAI-LDPC algorithm can obtain about 0.4 dB performance gain, and the average number of iterations is reduced by 68% under a low SNR. The algorithm can achieve better error-correcting performance and higher throughput, providing strong support for reliable transmission of satellite communications. [ABSTRACT FROM AUTHOR]

With the application of graph neural network (GNN) in the communication physical layer, GNN-based channel decoding algorithms have become a research hotspot. Compared with traditional decoding algorithms, GNN-based channel decoding algorithms have a better performance. GNN has good stability and can handle large-scale problems; GNN has good inheritance and can generalize to different network settings. Compared with deep learning-based channel decoding algorithms, GNN-based channel decoding algorithms avoid a large number of multiplications between learning weights and messages. However, the aggregation edges and nodes for GNN require many parameters, which requires a large amount of memory storage resources. In this work, we propose GNN-based channel decoding algorithms with shared parameters, called shared graph neural network (SGNN). For BCH codes and LDPC codes, the SGNN decoding algorithm only needs a quarter or half of the parameters, while achieving a slightly degraded bit error ratio (BER) performance. [ABSTRACT FROM AUTHOR]

In this work, we proposed a high-efficiency and low-complexity encoding algorithm and its corresponding implementation structure during the design and implementation process of an LDPC encoder and decoder. This proposal was derived from extensive research on and analysis of standard encoding algorithms and recursive iterative encoding algorithms, specifically targeting the problem of high computational complexity in encoding algorithms. Subsequently, we combined binary phase-shift keying modulation mode and additive white Gaussian noise channel transmission with the min-sum decoding algorithm to realize the (1536, 1024) LDPC codec. This codec was uniformly quantized with a (6, 2) configuration, executed eight iterations, and achieved a 2/3 code rate in the IEEE802.16e standard. At the bit error rate (BER) of 10 − 5 , the codec's BER obtained by the proposed coding algorithm was about 0.25 dB lower than the recursive-iterative coding algorithm and was about 1.25 dB lower than the standard coding algorithm, which confirms the correctness, effectiveness, and feasibility of the proposed algorithm. [ABSTRACT FROM AUTHOR]

In this article, a graph-theoretic method (taking advantage of constraints among sets associated with the corresponding parity-check matrices) is applied for the construction of a double low-density parity-check (D-LDPC) code (also known as LDPC code pair) in a joint source-channel coding (JSCC) system. Specifically, we pre-set the girth of the parity-check matrix for the LDPC code pair when jointly designing the two LDPC codes, which are constructed by following the set constraints. The constructed parity-check matrices for channel codes comprise an identity submatrix and an additional submatrix, whose column weights can be pre-set to be any positive integer numbers. Simulation results illustrate that the constructed D-LDPC codes exhibit significant performance improvement and enhanced flexible frame length (i.e., adaptability under various channel conditions) compared with the benchmark code pair. [ABSTRACT FROM AUTHOR]

We propose a distributed quasi-cyclic low-density parity-check (QC-LDPC) coded spatial modulation (D-QC-LDPCC-SM) scheme with source, relay and destination nodes. At the source and relay, two distinct QC-LDPC codes are used. The relay chooses partial source information bits for further encoding, and a distributed code corresponding to each selection is generated at the destination. To construct the best code, the optimal information bit selection algorithm by exhaustive search in the relay is proposed. However, the exhaustive-based search algorithm has large complexity for QC-LDPC codes with long block length. Then, we develop another low-complexity information bit selection algorithm by partial search. Moreover, the iterative decoding algorithm based on the three-layer Tanner graph is proposed at the destination to carry out joint decoding for the received signal. The recently developed polar-coded cooperative SM (PCC-SM) scheme does not adopt a better encoding method at the relay, which motivates us to compare it with the proposed D-QC-LDPCC-SM scheme. Simulations exhibit that the proposed exhaustive-based and partial-based search algorithms outperform the random selection approach by 1 and 1.2 dB, respectively. Because the proposed D-QC-LDPCC-SM system uses the optimized algorithm to select the information bits for further encoding, it outperforms the PCC-SM scheme by 3.1 dB. [ABSTRACT FROM AUTHOR]

A key component of the joint source-channel coding (JSCC) scheme based on double low-density parity-check (D-LDPC) codes is the introduction of a linking matrix between the source LDPC code and channel LDPC code, by which the decoding information including the source redundancy and channel state information can be transferred iteratively. However, the linking matrix is a fixed one-to-one mapping, i.e., an identity matrix in a conventional D-LDPC code system, which may not take full advantage of the decoding information. Therefore, this paper introduces a general linking matrix, i.e., a non-identity linking matrix, connecting the check nodes (CNs) of the source LDPC code and the variable nodes (VNs) of the channel LDPC code. Further, the encoding and decoding algorithms of the proposed D-LDPC coding system are generalized. A joint extrinsic information transfer (JEXIT) algorithm is derived for calculating the decoding threshold of the proposed system with a general linking matrix. In addition, several general linking matrices are optimized with the aid of the JEXIT algorithm. Finally, the simulation results demonstrate the superiority of the proposed D-LDPC coding system with general linking matrices. [ABSTRACT FROM AUTHOR]

In this paper, a joint group shuffled scheduling decoding (JGSSD) algorithm for a joint source-channel coding (JSCC) scheme based on double low-density parity-check (D-LDPC) codes is presented. The proposed algorithm considers the D-LDPC coding structure as a whole and applies shuffled scheduling to each group; the grouping relies on the types or the length of the variable nodes (VNs). By comparison, the conventional shuffled scheduling decoding algorithm can be regarded as a special case of this proposed algorithm. A novel joint extrinsic information transfer (JEXIT) algorithm for the D-LDPC codes system with the JGSSD algorithm is proposed, by which the source and channel decoding are calculated with different grouping strategies to analyze the effects of the grouping strategy. Simulation results and comparisons verify the superiority of the JGSSD algorithm, which can adaptively trade off the decoding performance, complexity and latency. [ABSTRACT FROM AUTHOR]

Recently, a mesh model-based merging (M 3 ) method and four basic graph models were proposed to construct the double protograph low-density parity-check (P-LDPC) code pair of the joint source channel coding (JSCC). Designing the protograph (mother code) of the P-LDPC code with both a good waterfall region and lower error floor is a challenge, and few works have existed until now. In this paper, the single P-LDPC code is improved to further verify the availability of the M 3 method, and its structure is different from the channel code in the JSCC. This construction technique yields a family of new channel codes with lower power consumption and higher reliability. The structured design and better performance demonstrate that the proposed code is hardware-friendly. [ABSTRACT FROM AUTHOR]

To meet the high throughput requirement of communication systems, the design of high-throughput low-density parity-check (LDPC) decoders has attracted significant attention. This paper proposes a high-throughput GPU-based LDPC decoder, aiming at the large-scale data process scenario, which optimizes the decoder from the perspectives of the decoding parallelism and data scheduling strategy, respectively. For decoding parallelism, the intra-codeword parallelism is fully exploited by combining the characteristics of the flooding-based decoding algorithm and GPU programming model, and the inter-codeword parallelism is improved using the single-instruction multiple-data (SIMD) instructions. For the data scheduling strategy, the utilization of off-chip memory is optimized to satisfy the demands of large-scale data processing. The experimental results demonstrate that the decoder achieves 10 Gbps throughput by incorporating the early termination mechanism on general-purpose GPU (GPGPU) devices and can also achieve a high-throughput and high-power-efficiency performance on low-power embedded GPU (EGPU) devices. Compared with the state-of-the-art work, the proposed decoder had a ×1.787 normalized throughput speedup at the same error correcting performance. [ABSTRACT FROM AUTHOR]

Considering the high compression requirements of transmission, lossy block codes are particularly concerned due to their good compression performance and simple implementation. This paper investigates and analyzes the distortion rate performance of protograph LDPC (P-LDPC) codes for Bernoulli sources over AWGN channels. We first analytically establish the connection between the parity check matrix of a P-LDPC code and the extra distortion caused by the noisy channels. It was found that the additional distortion related to channel noise increases with the rising total degree of a parity check matrix. Further, two design algorithms are proposed for optimizing lossy multirate P-LDPC codes, considering the effect of noisy channels. Finally, simulation results demonstrate the robustness of the optimized P-LDPC codes over noisy channels. [ABSTRACT FROM AUTHOR]

In order to improve the performance of non-binary low-density parity check codes (LDPC) hard decision decoding algorithm and to reduce the complexity of decoding, a sum of the magnitude for hard decision decoding algorithm based on loop update detection is proposed. This will also ensure the reliability, stability and high transmission rate of 5G mobile communication. The algorithm is based on the hard decision decoding algorithm (HDA) and uses the soft information from the channel to calculate the reliability, while the sum of the variable nodes' (VN) magnitude is excluded for computing the reliability of the parity checks. At the same time, the reliability information of the variable node is considered and the loop update detection algorithm is introduced. The bit corresponding to the error code word is flipped multiple times, before this is searched in the order of most likely error probability to finally find the correct code word. Simulation results show that the performance of one of the improved schemes is better than the weighted symbol flipping (WSF) algorithm under different hexadecimal numbers by about 2.2 dB and 2.35 dB at the bit error rate (BER) of 10-5 over an additive white Gaussian noise (AWGN) channel, respectively. Furthermore, the average number of decoding iterations is significantly reduced. [ABSTRACT FROM AUTHOR]

High-speed reconciliation is indispensable for supporting the continuous-variable quantum key distribution (CV-QKD) system to generate the secure key in real-time. However, the error correction process's high complexity and low processing speed limit the reconciliation speed. Therefore, reconciliation has also become the bottleneck of system performance. In this paper, we proposed a high-speed reconciliation scheme that uses the deep neural network to optimize the decoding process of the low-density parity-check (LDPC) code. We first introduced a network structure of decoding implementation based on the deep neural network, which can be applied to decoding algorithms of parallel strategy and significantly reduce the decoding complexity. Subsequently, we proposed two improved decoding algorithms based on this structure, named linear fitting algorithm and deep neural network-assisted decoding algorithm. Finally, we introduced a high-speed reconciliation scheme based on the CPU-GPU hybrid platform. Simulation results show that the proposed reconciliation scheme reduces the complexity and enables us to realize the high-speed CV-QKD system. Furthermore, the improved decoding algorithm can also reduce the FER, thereby increasing the secret key rate. [ABSTRACT FROM AUTHOR]

An efficient iterative timing recovery via steepest descent of low-density parity-check (LDPC) decoding metrics is presented. In the proposed algorithm, a more accurate symbol timing synchronization is achieved at a low signal-to-noise (SNR) without any pilot symbol by maximizing the sum of the square of all soft metrics in LDPC decoding. The principle of the above-proposed algorithm is analyzed theoretically with the evolution trend of the probability mean of the soft LDPC decoding metrics by the Gaussian approximation. In addition, an efficiently approximate gradient descent algorithm is adopted to obtain excellent timing recovery with rather low complexity and global convergence. Finally, a complete timing recovery is accomplished where the proposed scheme performs fine timing capture, followed by a traditional Mueller–Müller (M&M) timing recovery, which acquires timing track. Using the proposed iterative timing recovery method, the simulation results indicate that the performance of the LDPC coded binary phase shift keying (BPSK) scheme with rather large timing errors is just within 0.1 dB of the ideal code performance at the cost of some rational computation and storage. Therefore, the proposed iterative timing recovery can be efficiently applied on occasions of the weak signal timing synchronization in satellite communications and so on. [ABSTRACT FROM AUTHOR]

We design a decoding algorithm for linear codes over finite chain rings given by their parity check matrices. It is assumed that decoding algorithms over the residue field are known at each degree of the adic decomposition. [ABSTRACT FROM AUTHOR]

This paper deals with the specific construction of binary low-density parity-check (LDPC) codes. We derive lower bounds on the error exponents for these codes transmitted over the memoryless binary symmetric channel (BSC) for both the well-known maximum-likelihood (ML) and proposed low-complexity decoding algorithms. We prove the existence of such LDPC codes that the probability of erroneous decoding decreases exponentially with the growth of the code length while keeping coding rates below the corresponding channel capacity. We also show that an obtained error exponent lower bound under ML decoding almost coincide with the error exponents of good linear codes. [ABSTRACT FROM AUTHOR]

A potentially useful Cyber-Physical Systems element is a modern forward error correction (FEC) coding system, utilizing a code selected from the broad class of Low-Density Parity-Check (LDPC) codes. In this paper, development of a hardware implementation in an FPGAs of the decoder for Quasi-Cyclic (QC-LDPC) subclass of codes is presented. The decoder can be configured to support the typical decoding algorithms: Min-Sum or Normalized Min-Sum (NMS). A novel method of normalization in the NMS algorithm is proposed, one that utilizes combinational logic instead of arithmetic units. A comparison of decoders with different bit-lengths of data (beliefs that are messages propagated between computing units) is also provided. The presented decoder has been implemented with a distributed control system. Experimental studies were conducted using the Intel Cyclone V FPGA module, which is a part of the developed testing environment for LDPC coding systems. [ABSTRACT FROM AUTHOR]