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This paper presents CMOS and CNFET based hysteresis voltage comparators for low-voltage applications. The proposed CMOS and CNFET hysteresis comparators require merely 1.6 and 0.26 µW of power, respectively, which is less than one tenth of the power dissipated by the other advanced hysteresis comparators designs available in literature. The propagation delay observed in the proposed CMOS and CNFET hysteresis comparators are 162 and 47 ps, respectively, which is almost half the delay exhibited by the other hysteresis comparators. Overall, a 93–99% reduction in Power Delay Product (PDP) can be achieved. Furthermore, the proposed design requires only nine transistors compared to the 11–17 transistor requirement in conventional hysteresis comparators, thus saving up to 47% of chip area. [ABSTRACT FROM AUTHOR]

The XOR/XNOR gates are basic building blocks for various digital systems like adders, comparators, multipliers, parity-generator/checker and encryption processor. This paper proposes two realisations each using 2-pass transistors/2-transmission gates and 2-inverters. All the proposed circuits are simulated and compared with existing circuits using Cadence Spectre on both 180 and 90 nm CMOS technology with varying supply rail (from +0.8 V to +1.8 V). The simulation results confirm that the proposed circuits achieve a full rail-to-rail swing, high performance and high noise margin at low voltages. Analytical expressions in support of simulation-results wherever required are included. A typical application in Hamming-code generation is proposed. [ABSTRACT FROM AUTHOR]