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This paper experimentally validates a fully digitalized active gate driver for suppressing the switching surge voltage of SiC MOSFETs in a boost converter. High‐voltage power conversion systems are expected to adopt SiC unipolar power devices utilizing their high‐speed switching capability. The high‐speed switching operation causes the switching surge voltage in its switching transient. Active gate driving is a key technology for suppressing it. A fully digitalized active gate driver is particularly focused upon, which freely shaped the output gate‐source voltage waveform by a multi‐bit gate control signal. This driver achieves the dynamical control of the voltage/current behaviours of MOSFET in the switching transient by taking the Miller effect into account. It contributes to suppressing the switching surge voltage. This paper applies this digital active gate driver to a high voltage power conversion circuit. The switching surge voltage is experimentally suppressed by slew rate control with the digital active gate driver for various operating conditions. The results clarify the control strategy of the digital active gate driver for SiC MOSFET in a power conversion circuit. [ABSTRACT FROM AUTHOR]

Air‐stable semiconducting inks suitable for complementary logic are key to create low‐power printed integrated circuits (ICs). High‐performance printable electronic inks with 2D materials have the potential to enable the next generation of high performance low‐cost printed digital electronics. Here, the authors demonstrate air‐stable, low voltage (<5 V) operation of inkjet‐printed n‐type molybdenum disulfide (MoS2), and p‐type indacenodithiophene‐co‐benzothiadiazole (IDT‐BT) field‐effect transistors (FETs), estimating an average switching time of τMoS2 ≈ 4.1 μs for the MoS2 FETs. They achieve this by engineering high‐quality MoS2 and air‐stable IDT‐BT inks suitable for inkjet‐printing complementary pairs of n‐type MoS2 and p‐type IDT‐BT FETs. They then integrate MoS2 and IDT‐BT FETs to realize inkjet‐printed complementary logic inverters with a voltage gain |Av| ≈ 4 when in resistive load configuration and |Av| ≈ 1.4 in complementary configuration. These results represent a key enabling step towards ubiquitous long‐term stable, low‐cost printed digital ICs. [ABSTRACT FROM AUTHOR]

This article is a guest editorial that discusses advancements and future trends in noise radar technology. Noise radar technology uses random and non-periodic radar signals to eliminate ambiguities present in other radars. The article explores the practical aspects of noise radar technology, such as evaluating the degree of randomness in transmission and the computational load of signal processing. It also covers topics like electronic warfare, anti-intercept features, and the potential applications of artificial intelligence in noise radar technology. The article includes specific papers on implementation aspects, waveform selection, anti-intercept features, and artificial intelligence applications in noise radar technology. The authors hope that this special issue provides valuable insights into the advancements and future trends of noise radar technology. [Extracted from the article]

The UK net‐zero target requires the integration of significant renewable energy resources into the electrical grid. This, together with the projected growth in electricity demand imposes practical challenges on the power transfer capability of existing transmission feeders. For environmental and planning reasons, construction of new overhead lines is problematic, and where possible upgrading of existing substations and lines is preferred. This paper investigates the feasibility of transforming an existing three‐phase (3Φ) double‐circuit 400 kV line into a six‐phase (6Φ) feeder for a simulated future GB scenario. Results indicate a 6Φ feeder, operating at a 'phase‐adjacent phase' voltage of 400 kV can effectively solve the constraints of boundaries in transmission networks. When considering the various operating contingencies, associated with an important UK network boundary and its expected near‐future winter‐peak power transfer requirements, the thermal overload issues are mitigated by transforming a feeder from 3Φ to 6Φ. The paper demonstrates upgrading to 6Φ technology is a potential solution to certain future boundary constraints and in these cases avoids the need to build new underground or overhead AC/DC lines. [ABSTRACT FROM AUTHOR]

This paper proposes a small‐area and low‐power all‐digital duty cycle corrector with de‐skew circuit. By adopting the proposed delay unit containing a pre‐charge transistor, half cycle delay line can accurately generate half‐cycle delay, thus ensuring that the circuit can achieve duty cycle correction with small area and low power. To achieve high‐precision clock synchronization, the proposed de‐skew circuit utilizes a high‐resolution two‐stage digital control delay line to eliminate the additional clock skew between the input clock and output clock of the circuit. The test chip is fabricated in 130 nm CMOS process and the area only occupies 0.009 mm2. The chip testing results show that duty cycle correction error is within 3.2% and phase error is less than 16 ps when input duty cycle from 20% to 80% at the frequency range from 380 MHz to 1.25 GHz. And the proposed circuit only consumes 3 mW when supply voltage is 1.2 V and clock frequency is 1 GHz. [ABSTRACT FROM AUTHOR]

The large amount of secondary effects in complementary metal–oxide–semiconductor technology limits its application in the ultra‐nanoscale region. Circuit designers explore a new technology for the ultra‐nanoscale region, which is the quantum‐dot cellular automata (QCA). Low‐energy dissipation, high speed, and area efficiency are the key features of the QCA technology. This research proposes a novel, low‐complexity, QCA‐based one‐bit digital comparator circuit for the ultra‐nanoscale region. The performance of the proposed comparator circuit is presented in detail in this paper and compared with that of existing designs. The proposed QCA structure for the comparator circuit only consists of 19 QCA cells with two clock phases. QCA Designer‐E and QCA Pro tools are applied to estimate the total energy dissipation. The proposed comparator saves 24.00% QCA cells, 25.00% cell area, 37.50% layout cost, and 78.11% energy dissipation compared with the best reported similar design. [ABSTRACT FROM AUTHOR]

This document is a guest editorial from the journal Electronics Letters. It discusses the increasing use of digital techniques in analog integrated circuits and systems. The adoption of digital techniques is driven by the need to improve performance and meet the requirements of emerging applications such as Internet of Things (IoT) and biosensors. The editorial highlights recent advances in digital-based and digital-assisted integrated circuit design techniques in power management ICs, high-speed data conversion, and digital-assisted calibration. The authors also mention future developments in the field, including the integration of artificial intelligence and machine learning in analog processing and the use of digital-intensive solutions in future CMOS technology nodes and non-CMOS emerging technologies. [Extracted from the article]

With Cyber warfare, detection of hardware Trojans, malicious digital circuit components that can leak data and degrade performance, is an urgent issue. Quasi‐Delay Insensitive asynchronous digital circuits, such as NULL Convention Logic (NCL) and Sleep Convention Logic, also known as Multi‐Threshold NULL Convention Logic (MTNCL), have inherent security properties and resilience to large fluctuations in temperatures, which make them very alluring to extreme environment applications, such as space exploration, automotive, power industry etc. This paper shows how dual‐rail encoding used in NCL and MTNCL can be exploited to design Trojans, which would not be detected using existing methods. Generic threat models for Trojans are given. Formal verification methods that are capable of accurate detection of Trojans at the Register‐Transfer‐Level are also provided. The detection methods were tested by embedding Trojans in NCL and MTNCL Rivest‐Shamir‐Adleman (RSA) decryption circuits. The methods were applied to 25 NCL and 25 MTNCL RSA benchmarks of various data path width and provided 100% rate of detection. [ABSTRACT FROM AUTHOR]

The High‐Dynamic enhanced Loran (eLoran) signal simulator must accurately model the motion parameters and dynamic transmission delays of the carriers in the channel. A method was proposed based on B‐Spline interpolation, capable of arbitrary ratio interpolation and multi‐channel simulation. This method can regenerate carrier‐to‐transmitter distances from available discrete motion asynchronous data, it can effectively reproduce more motion details for carrier. The algorithm can be implemented using digital circuits, allowing for real‐time simulation on a hardware platform. The circuit structure is divided into integer and fractional calculations, which can satisfy the interpolation of asynchronous data with arbitrary ratios. Compared with existing methods, the approach simulates the motion parameters with satisfactory accuracy. [ABSTRACT FROM AUTHOR]

Uncore components such as on‐chip memory systems and on‐chip interconnects consume a large amount of energy in emerging embedded applications. Few studies have focused on next‐generation analytical models for future chip‐multiprocessors (CMPs) that simultaneously consider the impacts of the power consumption of core and uncore components. In this paper, we propose a convex‐optimization approach to design heterogeneous uncore architectures for embedded CMPs. Our convex approach optimizes the number and placement of memory banks with different technologies on the memory layer. In parallel with hybrid memory architecting, optimizing the number and placement of through silicon vias as a viable solution in building three‐dimensional (3D) CMPs is another important target of the proposed approach. Experimental results show that the proposed method outperforms 3D CMP designs with hybrid and traditional memory architectures in terms of both energy delay products (EDPs) and performance parameters. The proposed method improves the EDPs by an average of about 43% compared with SRAM design. In addition, it improves the throughput by about 7% compared with dynamic RAM (DRAM) design. [ABSTRACT FROM AUTHOR]

As one of the most critical blocks of the CMOS image sensor (CIS), the accuracy and power consumption of the analogue‐to‐digital converter (ADC) play an important role in its performance. However, due to the mutually restrictive relationship between power consumption and accuracy in the single‐slope ADC (SS ADC), it is difficult to improve these performance indexes meantime without an efficient optimal design method. Here, an optimal design methodology based on an improved artificial fish swarm optimization algorithm (IAFSOA) is proposed for a 10‐bit SS ADC in CIS. First, a voltage storage structure and offset calibration circuit are developed for promoting the performance of the comparator. Then, IAFSOA is developed for the circuit parameters optimization with faster convergence rate and higher computational accuracy. The proposed multi‐objectives optimization algorithm can obtain the optimal parameters of the kernel circuit components and lead to an enhancement of both power consumption and accuracy. The optimized SS ADC is designed based on 0.18 µm process to verify the effectiveness of the proposed method. Compared to the earlier reported work, the IAFSOA‐based optimal design method can promote the performance of the SS ADC by an improvement of effective number of bits and a reduction of power consumption. [ABSTRACT FROM AUTHOR]

Low‐frequency noise, generated inherently by the number or mobility fluctuation of carriers, is a crucial concern for the design of analog and digital circuits. Unified modelling based on experimental validation of near‐DC noise in amplifiers is a long‐standing open problem. This article develops a model for low‐frequency noise by deriving new bounds for carrier capturing and releasing. According to the proposed model, a measurement system is suggested that operates in a wide frequency range and even at very low frequencies. The system is noise‐tolerant, since the amplifier is selected based on acceptable noise levels. Among the advantages are the independence from specialized structural noise models for each component and the low cost of the measurement system. The evaluation results show that the proposed method leads to a promising improvement in the low‐frequency noise measuring and is superior to conventional models in the normalized root mean square error indicator. Findings reveal that the proposed measurement method can estimate the flicker noise around the DC frequency, and the proposed model agrees reasonably with the proposed measurement circuit. [ABSTRACT FROM AUTHOR]

This paper proposes a 250 mV supply voltage digital low-dropout (LDO) regulator. The proposed LDO regulator reduces the supply voltage to 250 mV by implementing with all digital circuits in a 0.11 µm CMOS process. The fast current tracking scheme achieves the fast settling time of the output voltage by eliminating the ringing problem. The over-voltage and under-voltage detection circuits decrease the overshoot and undershoot voltages by changing the switch array current rapidly. The switch bias circuit reduces the size of the current switch array to 1/3, which applies a forward body bias voltage at low supply voltage. The fabricated LDO regulator worked at 0.25 V to 1.2 V supply voltage. It achieved 250 mV supply voltage and 220 mV output voltage with 99.5% current efficiency and 8 mV ripple voltage at 20 µA to 200 µA load current. [ABSTRACT FROM AUTHOR]

This paper proposes a 250mV supply-voltrage digital low-dropout (LDO) regulator. The proposed LDO regulator reduces the supply voltage to 250mV by implementing with all digital circuits in a 0.11µm CMOS process. The fast current tracking scheme achieves the fast settling time of the output voltage by eliminating the ringing problem. The over-voltage and under-voltage detection circuits decrease the overshoot and undershoot voltages by changing the switch array current rapidly. The switch bias circuit reduces the size of the current switch array to 1/3, which applies a forward body bias voltage at low supply voltage. The fabricated LDO regulator worked at 0.25~1.2V supply voltage. It achieved 250mV supply voltage and 220mV output voltage with 99.5% current efficiency and 8mV ripple voltage at 20~200µA load current. [ABSTRACT FROM AUTHOR]

Computing‐in‐memory (CIM) is a promising technique for solving the 'memory wall' and 'power consumption wall' problems. However, calculations in the analog domain are limited in terms of accuracy and sensitivity to process, voltage, and temperature changes. In this study, the authors proposed a CIM multiply‐and‐accumulate (MAC) circuit in which the MAC result was reflected by the pulse edge and converted into the final digital output using a dual‐edge counter quantization circuit, thereby improving the accuracy of the MAC operation and reducing the difficulty of quantization. The performance of the proposed CIM circuit was evaluated using a 28‐nm process. It could achieve 4‐bit multiplication without errors, with an energy efficiency of 24.38 to 670.86 TOPS/W. [ABSTRACT FROM AUTHOR]

This article discusses the development of innovative flexible bioelectronics (FBEs) in the field of personalized health management, with a particular focus on cancer therapy. FBEs are portable electronic devices that integrate sensors into or combine with the human body to collect and manage personal health records. They can monitor biophysical and biochemical parameters, analyze bodily fluids for biomarkers, and provide insights into a patient's health at the molecular level. FBEs also have potential applications in disease intervention and treatment, such as nonpharmacological optical, electrical, and mechanical interventions. In the context of cancer therapy, FBEs can be used for early screening of tumor markers and for multimodal combination therapy. However, there are still challenges and problems to be addressed in the development of FBEs, including the need for innovations in functional materials, signal processing, biocompatibility, and device flexibility. Overall, FBEs have the potential to revolutionize personalized health management and contribute to the construction of innovative healthcare platforms. [Extracted from the article]

Modern electronic design automation (EDA) tools can handle the complexity of state‐of‐the‐art electronic systems by decomposing them into smaller blocks or cells, introducing different levels of abstraction and staged design flows. However, throughout each independently optimised design step, overheads and inefficiencies can accumulate in the resulting overall design. Performing design‐specific optimisation from a more global viewpoint requires more time due to the larger search space but has the potential to provide solutions with improved performanc. In this work, a fully‐automated, multi‐objective (MO) EDA flow is introduced to address this issue. It specifically tunes drive strength mapping, prior to physical implementation, through MO population‐based search algorithms. Designs are evaluated with respect to their power, performance and area (PPA). The proposed approach is aimed at digital circuit optimisation at the block level, where it is capable of expanding the design space and offers a set of trade‐off solutions for different case‐specific utilisation. We have applied the proposed multi‐objective electronic design automation flow (MOEDA) framework to ISCAS‐85 and EPFL benchmark circuits by using a commercial 65 nm standard cell library. The experimental results demonstrate how the MOEDA flow enhances the solutions initially generated by the standard digital flow and how simultaneously a significant improvement in PPA metrics is achieved. [ABSTRACT FROM AUTHOR]

A new low‐power and high‐speed multiplier is presented based on the voltage over scaling (VOS) technique and new 5:3 and 7:3 counter cells. The VOS reduces power consumption in digital circuits, but different voltage levels of the VOS increase the delay in different stages of a multiplier. Hence, the proposed counters are implemented by the gate‐diffusion input technique to solve the speed limitation of the VOS‐based circuits. The proposed GDI‐based 5:3 and 7:3 counters save power and reduce the area by 2x and 2.5x, respectively. To prevent the threshold voltage (Vth) drop in the suggested GDI‐based circuits, carbon nanotube field‐effect transistor (CNTFET) technology is used. In the counters, the chirality vector and tubes of the CNTFETs are properly adjusted to attain full‐swing outputs with high driving capability. Also, their validation against heat distribution under different time intervals, as a major issue in the CNTFET technology is investigated, and their very low sensitivity is confirmed. The low complexity, high stability and efficient performance of the presented counter cells introduce the proposed VOS‐CNTFET‐GDI‐based multiplier as an alternative to the previous designs. [ABSTRACT FROM AUTHOR]

Analog circuit design is comparatively more complex than its digital counterpart due to its nonlinearity and low level of abstraction. This study proposes a novel low‐level hybrid of the sine‐cosine algorithm (SCA) and modified grey‐wolf optimization (mGWO) algorithm for machine learning‐based design automation of CMOS analog circuits using an all‐CMOS voltage reference circuit in 40‐nm standard process. The optimization algorithm's efficiency is further tested using classical functions, showing that it outperforms other competing algorithms. The objective of the optimization is to minimize the variation and power usage, while satisfying all the design limitations. Through the interchange of scripts for information exchange between two environments, the SCA‐mGWO algorithm is implemented and simultaneously simulated. The results show the robustness of analog circuit design generated using the SCA‐mGWO algorithm, over various corners, resulting in a percentage variation of 0.85%. Monte Carlo analysis is also performed on the presented analog circuit for output voltage and percentage variation resulting in significantly low mean and standard deviation. [ABSTRACT FROM AUTHOR]

After decades of continuous scaling, further advancement of complementary metal‐oxide‐semiconductor (CMOS) technology across the entire spectrum of computing applications is today limited by power dissipation, which scales with the square of the supply voltage. Here, an atomic‐scale tin transistor is demonstrated to perform conductive switching between bistable configurations with on/off potentials ≤2.5 mV in magnitude. In addition to the low operation voltage, the channel length of the transistor is determined experimentally and with density‐functional theory to be ≤1 nm because the atoms instead of electrons are information carriers in this device. The conductance at on‐states of the bistable configurations varies between 1.2 G0 to 197 G0 (G0=2e2h−1, e stands for the electron charge and h for Planck's constant). Thus, the device can supply driving current from 1 to ≈375 µA in magnitude for logic circuits with the drain‐source dc voltage at decades of millivolts. The switching frequency of the atomic‐scale tin transistor has reached 2047 Hz. Furthermore, the on/off potentials in millivolts can reduce the energy consumption in the interconnects of integrated circuits at least by ≈400 times. Therefore, the atomic‐scale tin transistor has prospects in digital circuits with ultralow‐power dissipation and can contribute to the sustainability of modern society. [ABSTRACT FROM AUTHOR]

The safe and reliable operation of power converter requires a protection circuit with fast response when the power device is subjected to the short‐circuit (SC) fault. In addition, the on‐line condition monitoring circuit is beneficial to provide a suggestion for the replacement of aged device. The silicon carbide (SiC) power devices promise the higher power density in the system performance, but is still limited by the poor SC reliability issue. Thus, it is crucial to improve the robustness of SiC‐based power converter from the circuit design. This work proposes a novel gate charge detection circuit for SiC devices. It achieves a high‐speed SC protection against hard switching fault (HSF) based on the difference of Miller capacitance between normal condition and SC fault. Meanwhile, the condition monitoring is achieved based on the high gate leakage current of aged device. A high‐precision analog amplifier circuit is designed to acquire the gate signal. The normal/fault signal is distinguished and the protection is triggered using a digital‐controlled method to reduce the hardware cost. A 600‐ns SC response time is achieved, and the monitoring circuit can differentiate the aged device from the healthy one. [ABSTRACT FROM AUTHOR]

Quantum‐dot cellular automata (QCA) is a useful nano‐scale technology that uses less space and energy than complementary metal oxide semiconductor (CMOS) for circuits designing. Innovative digital automation continually strives for increased density while consuming very little power. QCA, which is based on Coulomb repulsion, is one of the most recent nanotechnologies. On the other hand, derived computing could serve as a useful prototype for energy‐efficient nano‐scale layouts. A multiplier is an important component of various digital circuits. On the basis of QCA, promising nanotechnology, a high‐speed and simple multiplier is constructed in this study. This research focuses on multiplier designs based on two‐bit Vedic multiplier mathematics. The authors use the QCADesigner‐E modelling environment to develop an ultra‐efficient and less complicated two‐bit Vedic multiplier with the assistance of the majority gate for low‐energy and high‐speed nanotechnology applications. Compared with other current structures, the suggested architecture has a reduced cell count and area. Furthermore, simulation findings showed that the suggested design is long‐term viable and may be utilized to implement complicated circuit designs for nano‐communication networks. [ABSTRACT FROM AUTHOR]

The latest efforts in digital fluidic circuits' research aim at being electronics‐free, light‐weight, and compliant controllers for soft robots; however, challenges arise to adjust the fluidic circuit's digital logic operations. Currently there is no other way to modulate the amplitude or frequency but to structurally redesign the entire fluidic circuitry. This is mainly because there is currently no method to create an analog circuit‐like behavior in the digital fluidic circuits using conventional digitized fluidic gates. In this work, a new approach is presented to designing a circuit with digitized fluidic gates that is comparable to an analog circuit capable of actively tuning the circuit's fluidic characteristics, such as pressure gain, amplitude of output, and time response. For the first time, a pressure‐controlled oscillator is modeled, designed, and prototyped that not only controls the fluidic oscillation, but also modulates its frequency using only a single, quasi‐static pressure input. It can also demonstrate the circuit's performance for the control of a soft robotic system by actively modulating the motion of a soft earthworm robot up to twice of crawling speeds. This work has distinct contributions to designing and building intelligent pneumatic controllers toward truly comprehensive soft robotic systems. [ABSTRACT FROM AUTHOR]

This study presents an 8‐bit delay line digital‐to‐time converter (DTC) with pre‐skewing and digital time interpolation. Pre‐skewing that lowers the per‐stage‐delay of delay lines beyond that set by the chosen technology is investigated. A cascode tri‐state inverter is proposed to improve the isolation between the input and output of interpolation cells so as to improve the linearity of the time interpolator. Design considerations that critically affect the linearity of the DTC are examined in detail. The impact of the slope of the inputs of the time interpolator on the latency and linearity of the interpolator is analysed and the maximum slope of the input of interpolators yielding the minimum latency without sacrificing linearity, is obtained. The timing errors of DTC are investigated and the considerations of the layout of the DTC are examined. The DTC is designed in a TSMC 65 nm 1.0 V CMOS technology and analysed using Spectre with BSIM3V3 device models. Post‐layout simulation results show the DTC offers 3.6 ps resolution, 580 MS/s conversion rate, and consumes 383 μW. [ABSTRACT FROM AUTHOR]

In the conventional airborne telemetry system, the pre‐modulation filter with a multi‐pole active Bessel filter is preferred to use in Pulse Code Modulator (PCM)/FM transmission. In the existing system, it is not possible to change the cut‐off frequency for different data rates dynamically as required in the launch scenario of a long‐range aerospace vehicle. In general, aerospace vehicle has multiple propellant stages to travel a desired trajectory path. Each stage gets separated from the vehicle at different instances. Each stage measurement plan is defined and correspondingly the PCM format is generated with an optimum data rate. Hence, the telemetry system is required to transmit variable data rates at various instances of a long‐range aerospace vehicle from launch point to end point of a vehicle. This can be addressed by designing a dynamically tuneable pre‐modulation (DTPM) filter. Here, a suitable DTPM filter scheme is proposed to mitigate variable data rate transmission in the telemetry system. The scheme is analysed as per IRIG‐106 standard and simulated using MATLAB. The same has been modelled using VHDL and implemented targeting 28 nm technology Xilinx Zynq FPGA device. [ABSTRACT FROM AUTHOR]

Adiabatic complementary metal–oxide–semiconductor (CMOS) circuits have been proposed as a low‐power option for CMOS systems‐on‐a‐chip (SoCs) but have not gained popularity due to practical difficulties in scaling to millions of gates. The architecture of a pipeline of stages with slow‐transitioning clock phases demands the generation and distribution of clock phases precisely and efficiently. This power must be more than offset by the power saved by using adiabatic circuits. The problems in adiabatic logic circuits are described, and solutions are proposed to address them. Three published topologies are considered, namely positive‐feedback adiabatic logic (PFAL), two‐level adiabatic logic (2‐LAL) and clocked adiabatic logic in 40 nm CMOS technology at 100 MHz. New circuit ideas for complete level restore in PFAL and avoidance of floating nodes in 2‐LAL are presented. The problem with 2‐LAL multi‐input gates is published and solved for the first time here using a modified PFAL. The conclusion is that a 3X power savings in PFAL is about the best that can be achieved in an SoC context—a low return given the required investments in area and complexity. This should motivate the future discovery of more efficient solutions. [ABSTRACT FROM AUTHOR]

The design and analysis of a low‐power multi‐band injection‐locked wireless receiver, implemented in complementary metal–oxide–semiconductor (CMOS) 130 nm technology, for wireless sensor network (WSN) applications are presented. The proposed receiver composed of an injection‐locked oscillator (ILO), low‐noise amplifier (LNA), and an envelope detector utilizes non‐coherent detection based on the frequency‐to‐amplitude conversion property of the injection‐locking phenomena. A lock range enhancement method is proposed through analytically and numerically determining the optimum biasing point of the injection transistor. The lock range of divide‐by‐4 super‐harmonic injection‐locking dictated by the third‐order non‐linear coefficient of the injection transistor is first investigated. The receiver applies divide‐by‐4, divide‐by‐2, and fundamental injection to demodulate the frequency‐shift‐key (FSK) and ON/OFF‐key (OOK) modulated signals from 433, 860–868, 902–928, 950–956, and 2360–2400 MHz frequency bands while keeping the power consumption in sub‐mW range. Post‐layout simulation results demonstrate that the proposed design achieves a maximum data rate of 5 Mbps for both FSK and OOK signals. With two modes of operation (high‐band and low‐band), the receiver consumes 762 and 675 μW of static power from a 0.7 V supply, achieving a sensitivity of −77 and −70 dBm at BER of 2 × 10−3. The FOMs for each mode are 152 and 135 pJ/b, respectively. [ABSTRACT FROM AUTHOR]

Carbon nanotube field‐effect transistors (CNTFETs) have been widely studied as a promising technology to be included in post‐complementary metal‐oxide‐semiconductor integrated circuits. Despite significant advantages in terms of delay and power dissipation, the fabrication process for CNTFETs is plagued by fault occurrences. Therefore, developing a fast and accurate method for estimating the reliability of CNTFET‐based digital circuits was the main goal of this study. In the proposed method, effects related to faults that occur in a gate's transistors are first represented as a probability transfer matrix. Next, the target circuit's graph is traversed in topological order and the reliabilities of the circuit's gates are computed. The accuracy of this method (less than 3% reliability estimation error) was verified through various simulations on the ISCAS 85 benchmark circuits. The proposed method outperforms previous methods in terms of both accuracy and computational complexity. [ABSTRACT FROM AUTHOR]

A nominative signature (NS) is a cryptographic primitive where two parties collude to produce a signature. It is a user certification system and has applications in a variety of sectors where nominee cannot trust heavily on the nominator to validate the nominee's certificate and only targeted entities are allowed to verify the signature on sensitive data. A new construction for NS from standard assumptions on lattice is provided. The authors' construction relies on collision‐resistant preimage sampleable function and symmetric key primitives like collision‐resistant pseudorandom function and zero knowledge proof system ZKB++ for Boolean circuits. The authors provide detailed security analysis and show that their construction achieves security under unforgeability, invisibility, impersonation, and non‐repudiation in the existing model. Furthermore, our construction exhibits non‐transferability. The security under non‐repudiation is achieved in the quantum random oracle model using Unruh transform to ZKB++. [ABSTRACT FROM AUTHOR]

The article discusses that breaking the traditional boundaries between analogue and digital in favour of an unified, cross-domain novel approach to future information processing. It mentions the engineering applications for computation and communication of this key result was one of the intuitions which started the digital revolution; and also mentions the boundaries between the analogue and the digital world have led to the development of Dyadic Digital Pulse Modulation (DDPM).

Two‐stage switch networks are an emerging design option for relatively small‐capacity space switches. They are classified into two categories: folded and unfolded. Although folded switches have been well studied, research on unfolded two‐stage switch networks (UTSNs) remains limited. Here, non‐blocking UTSNs are considered. First, a new UTSN design is presented that consists of input and output switch modules (ISMs and OSMs) using bidirectional switching techniques. The proposed UTSN is represented by B(n, m, r), where n, m, and r denote the number of input ports of the ISM, number of OSMs, and number of ISMs, respectively. Second, the maximum number of rearrangements for B(n, n, r) is proved to be ⌊(r−1)/2(n−1)⌋ in general, whereas it is limited to two when n ≥ r. The strictly non‐blocking condition for B(n, m, r) to be m ≥ n + 1 is also determined. Finally, it is shown that the switch hardware complexity becomes minimal at n=N/2 and saturates at N2/2 as N → ∞. [ABSTRACT FROM AUTHOR]

The architecture of a low‐leakage switch in complementary metal‐oxide‐semiconductor (CMOS) technology developed to implement long‐term analogue memories for low‐power applications is presented. The switch reduces the leakage current using a cascade of modified pass‐transistors without active circuits, thus producing a negligible power consumption. The technique is simple, modular, robust, and reduces the leakage current down to tens of aA at room temperature using a TSMC 0.18 µm technology. [ABSTRACT FROM AUTHOR]

This Letter proposes a new two-sample excess loop delay compensation in continuous-time delta-sigma modulators using time-shifted differentiated digital-to-analogue converter (DAC). This is done by using the information inherently available but ignored in the conventional methods, and therefore no additional hardware is required. Simulation results and mathematical analysis are provided to verify the effectiveness of the proposed structure. [ABSTRACT FROM AUTHOR]

This study deals with the performance analysis of three digital filters viz. multiple complex coefficient filter (MCCF), moving average (MA) and Butterworth in distribution static compensator (DSTATCOM) for non-linear loads. The filters are designed to extract the fundamental component of load current and tested in the closed-loop control of DSTATCOM. The filters are used to extract fundamental signal from the non-linear distorted source/load currents and all the lower-order harmonics present in the non-linear current drawn by the load. The performance of MCCF filter is compared to conventional filters such as Butterworth and MA filter. The detailed frequency response of MCCF is analysed. The magnitude and phase response plot of the MCCF suggest that this filter has unity gain and zero phase shift at fundamental frequency. All the three filters are implemented on a DSTATCOM for three-phase, three-wire distribution system. The DSTATCOM is implemented using a three-phase voltage source converter controlled using dSPACE 1104 controller. The closed-loop operation of DSTATCOM designed using MCCF is tested under steady state and dynamic system conditions. Simulation and experimental results are demonstrated with relevant waveforms under different load conditions. [ABSTRACT FROM AUTHOR]

This study presents a switchable bandpass circuit using a standard 0.18 μm complementary metal-oxide semiconductor (CMOS) and an integrated passive device (IPD) technology for fifth-generation (5G) mobile communications. The circuit consists of two IPD bandpass filters (BPFs) and one CMOS single-pole-double-throw switch for the 28 or 39 GHz bands. The broadband switch uses a body-float resistor to improve its insertion loss and power-handling capability. Moreover, the two rectangular ring BPFs not only achieve low losses but also feature good out-of-band rejections. The CMOS chip is then packaged on the IPD substrate with a footprint area of 5.4 mm2. The switchable filter results in 4.5/4.7 dB insertion loss, better than 35/30.1 dB isolation, and 18.5/17 dBm input P1 dB. [ABSTRACT FROM AUTHOR]

A third-order complex delta-sigma modulation (CDSM) structure with cross-coupling paths is proposed and analysed. Although the conventional CDSM can reduce circuits complexity in digital transmitter systems, it suffers from other shortcomings like increasing algorithm complexity. This structure imports cross-coupling paths both at output and interstage, which realises decorrelation between zeros and poles. The advantage is that complex zeros can be arbitrarily placed, and thus, the reconfigurable digital wireless transmitter application can be satisfied; and the poles are not affected by zeros placement, which improves the flatness of signal transfer function. [ABSTRACT FROM AUTHOR]

A simple and efficient linearisation front-end circuit for giant magnetoresistance (GMR) sensors are presented. This circuit essentially uses only a single opamp to linearise the (non-linear) GMR sensor output. A novel methodology that places an active GMR element, present inside the GMR sensor, in the feedback loop of the opamp is employed for linearisation. Initial validation of the front-end is performed using simulation and emulation studies. Then, the front-end, fabricated on a printed-circuit board, is interfaced with a GMR sensor. Experimentation showed output non-linearity is around 0.6%. The proposed front-end possess merits, like, low component-count and minimal error, no requirement of expensive amplifiers or matched resistors for linearisation, fast response, over the existing methods. [ABSTRACT FROM AUTHOR]

The high-precision time synchronisation is of vital importance in the modern communication, navigation system and weapon system. The microwave time transfer method is adopted to resolve the time synchronisation problem. After expounding the principle and system composition of the method, the microwave time transfer system has been constructed. First, the measurement of board-level and system was conducted. The transfer bandwidth in the experiment via microwave channel is 10 Mb. The results show that the jittering of retrieval signals via microwave channel is <4 ns. Then the microwave transmission experiment of 23 km was carried out. The results show that RMS error of time signal is <2 ns and the error between the forward and backward directions is <4 ns. [ABSTRACT FROM AUTHOR]

A novel FIR driver that can be applied to a low power mode in the (Low Power Double Data Rate 4) LPDDR4 standard has been developed. The proto-type transmitter architecture is implemented in 45 nm CMOS process and occupies 0.009 mm² area. The preemphasis tap weighting improves the eye opening by 27.9% vertically and 27% horizontally, respectively, and the transmitter consumes only 2.25 mW at 3.2 Gb/s. [ABSTRACT FROM AUTHOR]

A fully integrated broadband E-band power amplifier (PA) is implemented in 28 nm CMOS process. To enhance the output power (POUT), an 8-way differential series-parallel power combiner is used together with the neutralised bootstrapped cascode amplifier topology. The unit PAs are realised by bothNMOS and PMOS transistors, respectively, which cancel the amplitude-to-phase modulation (AM-PM) distortion due to non-linear gate-to-source capacitance (CGS) of NMOS and PMOS transistors under large input voltage amplitude. The presented PA achieves a saturated output power (PSAT) of 21.3 dBm with more than 18.5 GHz -3 dB small-signal bandwidth (BW-3 dB). [ABSTRACT FROM AUTHOR]

A power-efficient complementary voltage-to-time converter (CVTC) is proposed for a flash ADCs. The alternating reset direction according to the signal development direction reduces the power consumed by the reset operation and the operational frequency of the CVTC is effectively reduced by half. Accordingly, the logic circuits following the CVTC work in a time-interleaved manner, resulting in significant power saving. A 5-bit 2.5 GS/s flash ADC designed for a 40 nm CMOS process shows a 27% power reduction over the conventional voltage-to-time conversion-based flash ADC. [ABSTRACT FROM AUTHOR]

Three kinds of parameters are considered to speed up the read operation of phase change memory: bit line parasitic parameters, read transmission gate parasitic parameters and current mirror parasitic parameters. A set reference cell and a reset reference cell are used in the reference circuit. Simulated in 130 nm process, the read access time of 1-Mb phase change memory (PCM) is 6.7 ns. In Monte Carlo simulations, the worst read access time is 13.8 ns compared to conventional 85 ns. [ABSTRACT FROM AUTHOR]

A novel implementation is proposed to relax the specifications of the internal feedback path for a continuous-time delta-sigma modulator. A truncator is embedded into the digital excess loop delay (ELD) compensation path. Thermometer-coded truncation is achieved by reordering the reference voltages of the internal quantiser. This requires only a small amount of extra digital circuitry compared to the conventional digital ELD compensation. The digital encoder controlling the digital-to-analogue converter is simple, and it only introduces a small ELD. [ABSTRACT FROM AUTHOR]