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The International Maritime Organization (IMO) established new strategies that could lead to a significant reduction in the carbon footprint of the shipping sector to address global warming. A major factor in achieving this goal is transitioning to renewable fuels. This implies a challenge, as not only ship-innovative solutions but also a complete low-carbon fuel supply chain must be implemented. This work provides a method enabling the exploration of the potential of low-carbon fuel technologies for specific shipping routes up to larger sea regions. Several aspects including vessel sizes, impact of weather and shipping routes, emissions savings and costs are considered. The local energy use is determined with proven bottom-up prediction methods based on ship positioning data from the Automatic Identification System (AIS) in combination with weather and ship technical data. This methodology was extended by an approach to the generation of a basic low-carbon fuel system topology that enables the consideration of local demand profiles. The applicability of the proposed approach is discussed at hand via a case study on Roll-on/Roll-off passenger and cargo (RoPax) ferries transitioning from conventional fuels to a compressed hydrogen fuel system. The results indicate a potential reduction in emissions by up to 95% and possible system sizes and costs.

This paper discusses the application of resilience engineering principles by shipborne navigation systems. As a technological system, the ship navigation system comprises all the communication and navigation equipment required to operate a ship. If examined as a socio-technological system, one has to additionally consider the use of the ship navigation system by the bridge teams in order to perform the nautical profession in terms of safe and efficient ship navigation, taking into account environmental information received by communication. The first part of this work discusses the theoretical background of resilience engineering and situation awareness. Case studies are used to illustrate under which conditions the application of resilience principles may result in an improvement of the operational reliability. With the help of simulations, it is shown that a sub-optimal implementation and utilization of resilience principles may decrease the robustness of the technical ship navigation system, as well as the reliability and adaptability of the ship navigation system in use. The examples illustrate once again that monitoring is one of the four cornerstones of resilience: anticipating, monitoring, learning, and responding. This is due to the effectiveness of most resilience principles depending on the availability and trustworthiness of situational information in relation to system status and environmental conditions, irrespective of whether the generation and use of the situational information is machine-made or human-made. Therefore, the establishment of situation awareness is an essential accompanying functionality to be considered in design, operation, and use of resilient systems.

Orientador: Leandro Tiago Manera Tese (doutorado) - Universidade Estadual de Campinas, Faculdade de Engenharia Elétrica e de Computação Resumo: Projetos de conversores Analógico-Digitais com alta resolução, alta velocidade e consumo moderado se tornou dominante devido à demanda atual em tecnologias voltadas para comunicações em fio. No universo dos diferentes tipos de conversores, a arquitetura Pipeline, que faz uso de blocos de amostragem e retenção com a utilização de Buffers, vem se destacando por alcançar melhores resultados no que diz respeito à resolução na frequência de operação de 100 MHz, pois há uma vasta demanda de aplicações em equipamentos de uso militar e comercial que necessitam de aquisição de dados diretamente nesta banda. Quando os blocos destes circuitos projetados são construídos com Buffers bipolares em tecnologia BICMOS, eles podem atingir Spurious Free Dynamic Range (SFDR) menores que ?90 dB, ou seja, conseguem resoluções efetivas maiores que 14 bits. Entretanto, nas arquiteturas implementadas com a tecnologia CMOS utilizando o mesmo tipo de estrutura, este valor se limita a ?80 dB. Esta foi uma das principais alavancas que motivaram o desenvolvimento deste projeto, que envolve circuitos Buffers em tecnologia CMOS 0,35 µm. Desta forma, esta tese apresenta como objetivo principal o desenvolvimento de circuito Buffer em tecnologia CMOS que possa atingir Distorção Harmônica Total (THD) inferior a ?90 dB, operando na faixa de frequência de 100 MHz e com um nível de consumo relativamente baixo de 7 mW. Esta especificação de distorção permite propor a construção de blocos de amostragem e retenção com resoluções na ordem de 14 bits. Para isso, estudos de arquiteturas de malha aberta (open-loop) e circuitos realimentados são apresentados. Esta pesquisa, portanto, faz uso de análise matemática de pequenos ou grandes sinais com a finalidade de definir e quantificar os principais efeitos degradadores da linearidade tais como, o efeito de corpo, a modulação de canal, as capacitâncias parasitas e o efeito de carga. As técnicas de supressão, redução ou mesmo a compensação das fontes de erro supracitadas, que aparecem neste tipo de dispositivo, são empregadas na construção de cinco circuitos, sendo que uma dessas estruturas propostas faz o uso adicional do espelho de corrente na configuração Super Wilson. Um dos principais objetivos desta configuração é permitir a utilização de uma tensão de alimentação de menor amplitude, sem comprometer a excursão máxima do sinal. É importante destacar que, a principal meta no projeto do Buffer em CMOS foi alcançada. Um conjunto de medições experimentais foi realizado em todos os protótipos fabricados, confirmando que os projetos das arquiteturas aqui apresentadas podem dar uma contribuição modesta, porém importante para o estado da arte do projeto de Buffers na tecnologia CMOS Abstract: The design of Analog-to-Digital converters (ADC) with high resolution, high speed and moderate consumption became dominant due to its recent demand in wireless communications technologies. In the universe of different types of converters, the Pipelined architecture, which uses sample-and-hold blocks through the use of Buffers, stands out for achieving better resolution results related to the operating frequency of 100 MHz. This architecture has found many applications in both military and commercial equipment where data acquisitions in this frequency range are necessary. When the designed circuit blocks are constructed with bipolar buffers in BICMOS technology, they can achieve Spurious Free Dynamic Range (SFDR) less than ?90 dB, i.e. they can reach effective resolutions higher than 14 bits. However, in the architectures implemented in CMOS technology using the same type of dedicated electronic structure (SHA), this value is limited to ?80 dB. This was one of the main reasons that motivated the development of this thesis involving Buffers circuits in 0.35 µm CMOS technology. Desta forma, esta tese apresenta como objetivo principal o desenvolvimento de circuito Buffer em tecnologia CMOS que possa atingir Distorção Harmônica Total (THD) inferior a ?90 dB, operando na faixa de frequência de 100 MHz e com um nível de consumo relativamente baixo de 7 mW. Esta especificação de distorção permite construir de blocos de amostragem e retenção com resoluções na ordem de 14 bits. In this work, a Buffer circuit operating in the frequency range of 100 MHz, with a relatively low power consumption of 7 mW and a Total Harmonic Distortion (THD) lower than - 90 dB has been achieved. This distortion specification allows proposing the sample-and-hold blocks design with resolutions on the order of 14 bits. In order to get to these results, studies of open-loop circuits and closed-loop circuits were performed. In this way, this work has used mathematical analysis of small and large signals in order to define and quantify the main effects that degrades the circuit¿s linearity, such as the body effect, channel modulation, the effect of parasitic capacitances and the load effect. By using techniques for the elimination, reduction or offsetting these sources of error above-mentioned, which appear in this type of device, a design of five new circuits were obtained; one of these proposed structures make use of the Super Wilson current mirror. The main goal of this configuration is to allow the use of a lower supply voltage, without compromising the maximum signal excursion. It is important to highlight that the main goal in the CMOS buffer design has been achieved. A set of experimental measurements was performed in all prototypes, confirming that the design of such new architectures presented in this work can provide a modest contribution, but important to the state of the art of Buffer in CMOS technology Doutorado Eletrônica, Microeletrônica e Optoeletrônica Doutor em Engenharia Elétrica