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High-quality InN has significant opportunities for exciting and impactful electronic and photonic applications. These applications rely on growth techniques that produce high-quality InN thin films. To achieve the fabrication of InN semiconductor thin films with a low density of misfit and threading dislocations, we report on a growth technique that utilizes composition and strain gradients to limit the propagation of defects into InN grown on a GaN/sapphire substrate. The growth technique we have investigated utilizes a compressively strained gradient transition layer to limit the propagation of threading dislocations from the GaN buffer. Reflection high-energy electron diffraction, high-resolution X-ray diffraction, Raman spectroscopy, photoluminescence, and Hall measurements were employed to evaluate the effectiveness of the gradient transition layer to improve the quality of InN thin films. The outcome is that for InN films grown on partially graded InxGa1–xN (x→ 0 to 29%), when compared with InN grown directly on a GaN substrate, we observed about a 40% decrease in edge dislocations, a 50% increase in photoluminescence, and a 20% increase in mobility. When compared to a sharp strain boundary, a linear strain gradient offers threading dislocations the opportunity to reduce the energy of the system more by leaving the system than by propagating into the strained region.

This article introduces a holistic and systematic design methodology tailored to the 10 kV silicon carbide (SiC) mosfet power modules. Multiobjective optimization was achieved with enhanced electric-field (E-field) distribution, minimized common-mode (CM) parasitic capacitance, and reduced system-level parasitic inductances. The proposed approach encompasses two innovative techniques: 1) an electric-potential-oriented module-system interface to reduce system-level parasitic inductance while maximizing insulation capability; 2) stacked substrates with patterned middle layer copper to alleviate the E-field concentration at the triple-point and reduce the maximum E-field without compromising on thermal resistance. The effectiveness of these innovative approaches is substantiated through the development of a 10 kV SiC mosfet power module. The optimized layout presents well-balanced 5.6 nH power loop inductance with embedded decoupling capacitors and record-low 28 pF CM parasitic capacitance, attributed to the middle layer pattern structure. In addition, a 38.6% E-field concentration reduction at the triple-point is identified compared to conventional stacked substrates. Experimental validation showcases its robust voltage insulation capability with a leakage current of 0.87 μA at 10 kV, a 33 kV dc, and 25 kV ac surface flashover for worst-case system fault conditions. The partial discharge inception voltage of the proposed middle layer patterned stacked substrates is verified at 16.8 kVrms. Dynamic performance validation through a double-pulse test at 5 kV showcases negligible ringing and voltage overshoot. All these exceptional attributes position the packaged 10 kV SiC mosfet power module as an exemplary choice for MV power electronics applications.

We report for the first time on an aluminum nitride/gallium nitride (AlN/GaN) heterostructure as a microscale Hall effect sensor for current sensing applications in extreme environments. The AlN/GaN devices demonstrated high signal linearity as a function of the magnetic field across a temperature range from -193 °C to 407 °C. The measured room temperature (RT) supply voltage-related sensitivity ( ${S}_{\text {svrs}}{)}$ and supply current-related sensitivity ( ${S}_{\text {scrs}}{)}$ are 0.055 T-1 and 32 AV-1T-1, respectively. The supply power-related sensitivity ( ${S}_{\text {sprs}}{)}$ is 1.4 VW-1T-1 above 40-mW input bias, which is higher than that of the Al0.2Ga0.8N/GaN device. The designed AlN/GaN micro-Hall sensor is further determined to have a lower power consumption and higher temperature sensitivity than equivalent Al0.2Ga0.8N/GaN Hall devices. When operated in an ac bias mode, the rise time of the Hall sensor was found to be 102 ns, corresponding to a frequency bandwidth of 9.8 MHz. We also observed a phase shift between an applied magnetic field and the Hall sensor signal, which can potentially be helpful to monitor ac line currents.

Silicon carbide (SiC) power devices have been extensively for high-power-density application scenarios. To increase the current rating, SiC devices are usually connected in parallel. However, the mismatching current brought by unbalanced electrical parameters can increase the current stress of a device and pose a reliability concern for the converter system. Aiming at addressing the current imbalance for paralleled SiC devices, this article reports the application of an improved active gate driver (AGD) on the paralleled SiC MOSFETs to address the current imbalance problems. The three-level driver voltage can minimize the overshoot voltage and current. The adjustable turn-on voltage and gate signal delay time can realize the current sharing of both static and dynamic processes. Current sensors and a digital controller are utilized for close-loop control. The functionality of the proposed AGD is validated in continuous operating experiments.

Recent studies in power electronic design automation have introduced various models for parasitic extraction of multichip power module layouts. However, none of these studies considers the eddy current effect in the direct-bonded-copper substrate, accounting for 40%–50% errors in the extraction result. This work introduces a methodology for eddy-current consideration through numerical simulation and regression modeling. The regression model utilized in the characterization process in this work is fast and memory-efficient compared to the finite element approach. This characterization process can improve the accuracy of any partial element model without sacrificing performance. Combining this characterization process and partial element approach achieves less than 10% extraction error compared to Ansys Q3D while showing a maximum speedup of $35\times $ and $17\times $ more memory efficiency. This method also significantly reduces the number of elements in the extracted netlist and the complexity of loop evaluation. This method is attractive for use with optimization routines and, therefore, has been used successfully in a layout optimization tool.