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The method for modeling switching converters plays a key role in real-time simulators. Associate discrete circuit (ADC) modeling technique is a commonly used method for modeling the switching converter. However, the optimal selection of the ADC-based switch model parameters has great importance in the accuracy of the real-time simulator. In this paper, the design of a real-time simulator for a switching power converter has been done, in which a novel method for detecting optimum values of the switch model parameters has been expressed. Particle swarm optimization (PSO) algorithm is used to find these optimum values using state-space analysis of the modeled circuit in the z-domain. The modified nodal analysis (MNA) method solves the real-time model at each simulation time-step. Case studies are a single-phase 5-level Cascaded H-Bridge (CHB), three-phase 9-level CHB inverter, and a Transmission line. Field-programmable gate array (FPGA) has been used as a platform for implementing the real-time simulator. Experimental result of the real-time simulator of the 5-level CHB inverter on a SPARTAN-6 FPGA and its comparison with the result of a prototype of a 5-level CHB inverter confirms not only the performance of the real-time simulator, but also the effectiveness of the proposed method for confirming the real-time simulator accuracy. [ABSTRACT FROM AUTHOR]

This paper introduces hybrid iterative algorithms that combine Particle Swarm Optimization (PSO) and Simulated Annealing (SA) algorithms for Field Programmable Gate Array (FPGA) placement by considering adaptive inertia weight and local minima avoidance. The algorithms target to optimize the wire-length of the nets, run time and critical path delay in the placement of logic blocks. Using the adaptive inertia weight parameter and local minima avoidance, the hybrid PSO-SA algorithm is modified to Time-varying PSO-SA (TPSO-SA) and Modified PSO-SA (MPSO-SA) algorithm, respectively. These different hybrid PSO-SA algorithms are checked for efficiency by comparing with the Versatile Place and Route (VPR) algorithm of the Verilog to Routing (VTR) tool using Microelectronics Centre of North Carolina (MCNC) benchmark circuits. The hybrid PSO-SA algorithms give 5–37% better results for wire-length cost and 20–58% reduction in runtime compared to the VPR placement algorithm on different benchmark circuits. Critical path delay is also taken into consideration. [ABSTRACT FROM AUTHOR]