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Gallium nitride (GaN) devices are generally more prone to severe switching oscillations than Si mosfets due to their fast switching speeds. Different from Si and SiC mosfets, GaN devices typically have a lower maximum gate voltage rating. Taking the Efficient Power Conversion Corporation series as an example, the gate drive voltage is usually 5 V, but the maximum voltage rating is 6 V. Therefore, GaN devices are more susceptible to damage from gate-source voltage oscillation. In this letter, a gate drive circuit with a clamping function is proposed to suppress gate-source voltage oscillation. The adopted method can not only clamp the gate voltage of the GaN device near the drive voltage to protect the device, but also does not affect the switching speed of the device. The proposed method mainly uses some passive components that make the circuit design simpler compared with other active gate driver methods. Finally, the effectiveness of the proposed method is verified by experiments. [ABSTRACT FROM AUTHOR]

This article puts forward a hybrid model predictive control (H-MPC) for an inner-interleaved hybrid multilevel converter (IHMC). The sign patterns of the original and shifted reference vectors in the original and virtual space vector diagrams (VSVDs) are used, respectively, to realize the phase-disposition pulsewidth modulation (PWM) and determine the low-frequency switching states. Then, the three adjacent vectors are selected in the second-layer VSVD and the optimal current tracking is safeguarded by the duty cycle optimization of the three adjacent vectors. Finally, through applying the phase-shifted PWM to the two interleaved legs, a constant and doubled equivalent switching frequency can be achieved, which further paves the way for dc-link and floating capacitor voltages balancing and circulating current mitigation with the use of the straightforward duty cycle adjustments. The proposed H-MPC enables the decoupling of the low- and high-frequency stages in the IHMC and also reduces both output current ripples and computational burden while achieving a constant switching frequency simultaneously. Comprehensive simulation and experimental studies on an all silicon carbide prototype verify the effectiveness of the proposed control strategy. [ABSTRACT FROM AUTHOR]

This article puts forward a hybrid model predictive control (H-MPC) that enables the decoupling of low- and high-frequency stages in a seven-level hybrid multilevel converter (7L-HMC). It first uses the sign pattern of the reference voltage vector to determine switching states of the low-frequency stage. Next, the reference vector is shifted to the internal hexagon of the original space vector diagram, which is thereby converted to a 120° oblique coordinate system, where the adjacent vectors can be rapidly selected. Then, the optimal current tracking is primarily safeguarded by the duty cycle optimization of the three adjacent vectors. Finally, an optimized symmetric switching sequence minimizing the dc voltage deviation over one control iteration is selected through the assessment of possible switching sequences that are subject to the chosen vectors with optimal duty cycles. The proposed H-MPC method can reduce both the current ripple and computational burden while achieving a constant switching frequency. Comprehensive simulation and experimental comparisons on an all-silicon-carbide 7L-HMC prototype verify the effectiveness of the proposed H-MPC. [ABSTRACT FROM AUTHOR]

This article presents the design and demonstration of an all silicon carbide (SiC) 2×250 kW dual inverter for heavy-duty traction applications. Through the use of a formal electrothermal-control co-design approach, the maximum power density of the proposed inverter system is 60 kW/L, which is accomplished by. More specifically, to analyze the thermal performance of the inverter, a lumped thermal model is developed based on the characteristics of the power modules and the cold plate. To analyze the complicated interaction between the power losses and module junction temperatures, a closed-loop iterative estimation scheme is proposed to estimate the inverter power loss and module junction temperature. Based on the proposed thermal model and estimation scheme, a detailed optimization procedure on the selection of switching frequency and dc-link capacitor is presented to maximize power density. Furthermore, design optimization of the busbar was conducted to minimize the stray inductance, thus reducing the voltage overshoot during switching transients. Comprehensive experimental studies were performed on a physical converter prototype built based on the optimization results, which validate both the effectiveness of the presented design approach. [ABSTRACT FROM AUTHOR]

The silicon carbide (SiC) devices have faster switching speed than that of the conventional silicon (Si) devices, which however may cause excessive device voltage overshoot. Larger gate resistance can help to restrain the overshoot, it however slows down the switching speed and increases switching losses. There are other methods that can mitigate the voltage overshoot, e.g., using low-inductance busbars, adding snubber circuits, etc. In this article, the busbar design for a 250-kW SiC three-level T-type inverter is investigated. The current commutation loops (CCLs) are first analyzed using a single-phase equivalent circuit. Then the detailed busbar design methods, especially a 3-D busbar design concept, are proposed to select the optimal stacking order for the multilayer laminated busbar and to address constraints posed by the physical terminal arrangements of SiC modules and dc-link capacitors. The stray inductance in each CCL is extracted via a finite element analysis and validated on the actual inverter busbar prototypes using an impedance analyzer. To further minimize the busbar stray inductance, a hybrid busbar structure with printed circuit board based buffer circuit using high-frequency decoupling capacitors is designed and evaluated in this article. Finally, the effectiveness of the designed busbars as well as the buffer circuit are validated using experimental studies. [ABSTRACT FROM AUTHOR]

The cascaded H-bridge (CHB) inverter is one of the most attractive multilevel topologies for renewable energy applications. Due to the fact that CHB inverters employ a large number of components, they suffer from a higher probability of fault, which reduces the system reliability. A fault-tolerant operation for a CHB inverter is described in this article. New features ensure reliable and robust operation of the converter in the event of a fault. The proposed strategy uses an additional cross-coupled CHB (X-CHB) unit in companion with the existing CHB units to support the output voltage and ensure continuity of operation in the event of an open/short-circuit fault. The operation of the proposed X-CHB inverter is described in detail. Simulation and experimental verification of the proposed concept are demonstrated using a seven-level CHB. Both simulation and experimental results confirm the fault-tolerant operation of the X-CHB for a battery energy storage system in case of switch faults. [ABSTRACT FROM AUTHOR]

This paper presents a practical strategy for utilizing the submodule (SM) redundancy of a modular multilevel converter (MMC) for its fault tolerance. This strategy provides a systematic framework for balancing the tradeoff between two conventional methods for using the active redundancy and, thus, achieves operational flexibility. One of the existing methods improves SM reliability owing to less voltage stress on the SM components by employing all of the SMs to form the ac or dc voltages (voltage-sharing mode). The other avoids transients by keeping the average SM voltage constant at the cost of slightly increased stress on the SM components (fixed-level mode), which, however, can be controlled to provide the grid-adaptive operation by reserving the energy of the SMs not in service. We, thus, develop a new redundancy management scheme by integrating these two methods and exploiting their technical benefits to meet the PQ requirements and MMC control performance. This research provides a theoretical basis and a technical guide to determining the number of SMs, which can further increase the voltage steps as per the MMC and grid conditions. This paper also connects the remaining PQ capability of the MMC at a particular operating point with the SM redundancy concept by defining a potential redundancy, especially useful when the physical redundancy is exhausted. The theoretical findings and efficacy of the proposed strategy are validated through PSCAD/EMTDC time-domain simulations followed by experiments using a nine-level single-phase MMC system. [ABSTRACT FROM AUTHOR]

This paper describes a silicon carbide pulse width modulation (PWM) signal generator in the 1.2 μm HiTSiC CMOS process developed by Raytheon Systems Ltd. The design features a 6-b binary input, which allows for setting a system's duty cycle. The results presented in this paper utilize a field programmable gate array board in the test setup to dynamically set the duty cycle by controlling each bit. A control current is also available to give the user added flexibility for tuning the duty cycle. Experimental results show the duty cycle range of the PWM generator to be between 4.7% and 95.2% at 400 °C. Sustained operation of the circuit is demonstrated over a period of 50 h at 300 °C. Finally, the PWM generator is evaluated in the operation of a boost converter. [ABSTRACT FROM PUBLISHER]