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Varistors are widely used in dc circuit breaker (DCCB) application as fault energy absorption elements, which is not an application the varistors are originally designed for. The fault energy stress adversely impacts the varistor lifetime, thus affecting DCCB reliability and performance. This article presents two methods for choosing the appropriate varistor type and arrangement in a DCCB by linking 1) varistor lifetime and 2) DCCB component- and system-level parameters. The first method uses a set-based design approach with random Latin hypercube sampling to narrow down viable solutions. In comparison, the second method relies on a point-based design approach and proposes an integer programming problem to optimize varistor lifetime. Both procedures are applied to the selection of varistors in 1) a 12 kV DCCB rated for 2-kA nominal current and a peak fault current of 15 kA and 2) a reduced-scale 1.2-kV DCCB hardware prototype, using publicly available varistor data. The article shows the possibility of design for varistor lifetime in DCCB applications, and concludes that both selection procedures provide consistent, reasonable, and verifiable results. However, the results also pinpoint the significant gaps and call for future work on impulse stress versus lifetime relationships for DCCB varistors. [ABSTRACT FROM AUTHOR]

This paper proposes a time-domain method to calculate the fault response in multiterminal dc (MTdc) grids and the performance of hybrid dc breakers. The proposed method, based on traveling waves: 1) provides a sound representation of fault performance by considering all created traveling waves; 2) introduces a new approach to estimate the reflection coefficients; and 3) provides an approximation of the worst case fault location. Then, based on the analytical results, three parameters of the hybrid dc circuit breaker, i.e., current limiting reactor, arrester rated voltage, and time delay are optimally selected with respect to maximum overcurrent, maximum overvoltage, fault clearance time, and energy absorption in arresters through multiobjective optimization. Accuracy and performance of the proposed method are evaluated and verified by time-domain simulation studies in the power systems computer aided design (PSCAD)/electromagnetic transients including DC (EMTDC) environment using frequency-dependent models. The results confirm reasonable accuracy of the proposed fault performance calculation and represent a further step towards optimized design of hybrid dc circuit breakers. [ABSTRACT FROM AUTHOR]

A sequential switching strategy for hybrid dc circuit breaker (CB) is proposed to improve transients during dc fault interruption in multiterminal high voltage direct current (HVdc) grids. Compared to the conventionally tripped dc CB, the proposed switching strategy, which sequentially trips the breaking modules within the CB, reduces the peak fault current and overvoltage as well as fault clearance time. These metrics are analytically computed through a time-domain calculation approach considering the traveling wave phenomena in dc transmission systems. By rescheduling the tripping sequence and optimal rating and number of individual modules of the CB, the energy distributed among the modules is well balanced. Finally, an analytic evaluation of the proposed sequential tripping is performed and, subsequently, the best practice and the optimal design process are provided. Performance of the sequential switching strategy as well as the optimal design process are verified through simulation studies in the PSCAD/EMTdc software environment. [ABSTRACT FROM AUTHOR]

Protection against dc faults is one of the main technical challenges for the operation of converter-based HVdc systems. Protection becomes even more challenging when the HVdc systems are expanded to multi-terminal dc (MTdc) grids with more than two terminals/converter stations. Similar to their ac counterparts, proper protection of the MTdc grids necessitates both primary and backup protection schemes in which, in case of malfunctioning/failure of primary protection, backup protection trips as fast as possible. Although several backup relaying algorithms, such as current threshold- and classifier-based methods, have been proposed, none of them offers sufficient speed, robustness, and scalability. In this paper, a novel backup protection algorithm based on quickest change detection technique is proposed, which offers fast and robust backup protection functionality for the primary relay. The performance and effectiveness of the proposed algorithm are evaluated and verified with time-domain simulation studies in the PSCAD/EMTDC environment. The study results confirm satisfactory performance of the proposed algorithm in terms of accuracy, robustness, and speed under various fault scenarios. The proposed method is applicable to different grid configurations and is able to cooperate with different primary protection algorithms and breaker configurations. [ABSTRACT FROM AUTHOR]

The modular multilevel converter (MMC) has become the most promising converter technology for high-voltage direct current (HVDC) transmission systems. However, similar to any other voltage-sourced converter-based HVDC system, MMC-HVDC systems with the half-bridge submodules (SMs) lack the capability of handling dc-side short-circuit faults, which are of severe concern for overhead transmission lines. In this paper, two new SM circuit configurations as well as a hybrid design methodology to embed the dc-fault-handling capability in the MMC-HVDC systems are proposed. By combining the features of various SM configurations, the dc-fault current path through the freewheeling diodes is eliminated and the dc-fault current is enforced to zero. Several MMC configurations based on the proposed hybrid design method and various SM circuits, that is, the half-bridge, the full-bridge, the clamp-double, and the five-level cross-connected SMs, as well as the newly proposed unipolar-voltage full-bridge and three-level cross-connected SMs, are investigated and compared in terms of the dc-fault-handing capability, semiconductor power losses, and component requirements. The studies are carried out based on time-domain simulation in the PSCAD/EMTDC software environment for various SM configurations and dc-fault conditions. The reported study results demonstrate the proposed hybrid-designed MMC-HVDC system based on the combination of the half-bridge and the proposed SM circuits is the optimal design among all evaluated systems in terms of the dc-fault-handing capability, semiconductor power losses, and component requirements. [ABSTRACT FROM PUBLISHER]