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Coarse grain reconfigurable architectures (CGRAs) are an emerging hybrid computational architecture that has the parallel customization benefits of low-level logic devices, such as FPGAs and ASICs, while the relative coarseness of these architectures makes CGRAs easier to design for, which is more similar to the traditional processor. In the process of mapping designs to CGRAs, flexible, fast, and adaptive placement and routing (P&R) is fundamental in order to implement efficient run-time reconfigurable frameworks. It is well-known that P&R is an NP-complete problem, and thus, solutions rely on heuristics to achieve quality results with acceptable execution times. CGRA P&R has different constraints compared to traditional VLSI P&R, e.g., path latency balancing and modulo scheduling of loops. In this work, we propose a graph-based P&R approach that uses graph traversals to map designs to CGRAs. Additionally, we parallelize our approach with a graph-based greedy heuristic that executes on a GPU. We compare our proposed P&R approach with the CGRA-ME framework, which implements simulated annealing and integer linear programming placement algorithms. Our results show that this new approach can generate optimal mappings and improve the execution run-time up to several orders of magnitude. Furthermore, considering spatial mapping at the millisecond scale, our GPU approach is one order of magnitude faster compared to the state-of-the-art tool VPR. [ABSTRACT FROM AUTHOR]

Quantum-dot cellular automata (QCA) is an emerging technology, conceived in face of nanoscale limitations of CMOS circuits, with exceptional integration density, impressive switching frequency, and remarkable low-power characteristics. Several of the current challenges toward the progress of QCA technology is related to the automation of the design process and integration into existing design flows. In this regard, this paper proposes the universal, scalable, efficient (USE), and easily manufacturable clocking scheme. It solves one of the most limiting factors of existing clock schemes, the implementation of feedback paths and easy routing of QCA-based circuits. Consequently, USE facilitates considerably the development of standard cell libraries and design tools for this technology, besides avoiding thermodynamics problems. Case studies presented in this paper reveal an area reduction of up to factor 5 and delay decrease by up to factor 3 in comparison with an existing advanced clocking scheme. [ABSTRACT FROM PUBLISHER]