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This article proposes a systematic synthesis method to identify the optimum converter topology for a specified voltage conversion ratio. This gain-oriented converter synthesis is formulated as an inverse problem around the inductor flux balance equations. The proposed synthesis method consists of two processes. A set of distinct converter topologies is first synthesized from the specified voltage conversion ratio by obtaining the solutions for a set of six inverse equations in twelve unknowns. The optimal topology for any intended application can be identified based on the desired performance metrics. The complete synthesis method is illustrated with quadratic buck–boost gain as an example. In total, 25 distinct topologies are synthesized using the first process, and their feasibility is validated by PLECS simulation. In total, three case studies are reported to explain the second process. Ground-referenced output and the minimum number of switches are used as the first two selection criteria in all the case studies. Minimum peak inductor current, minimum component stress factor, and minimum voltage and current stress are the third selection criterion in Case Studies-1, 2, and 3, respectively. The steady-state operations of two optimal converters selected in Case Study-1 were verified experimentally. [ABSTRACT FROM AUTHOR]

This article presents an analytical method to derive an optimum converter topology for a specified voltage conversion ratio (G). An optimum topology for any given G can be identified after obtaining the comprehensive pool of converter topologies. This gain-oriented converter synthesis is formulated as an inverse problem around the principle of inductor flux balance. A step-by-step method is proposed to solve the inverse problem and obtain a comprehensive set of non-redundant converter topologies for any given voltage conversion ratio. Consequently, the number of possible converter topologies for a specified voltage conversion ratio is also identified. The optimum converter topology is chosen from the comprehensive set based on three selection criteria, viz., ground-referenced output, a minimum number of switches, and minimum peak inductor current. The proposed solution methodology is illustrated with quadratic boost and quadratic buck gains as case studies. A comprehensive set of non-redundant topologies is identified in both cases. The steady-state operations of all the topologies are studied with PLECS simulation. Based on the selection criteria, an optimum topology is selected in each case, and their steady-state operation is verified experimentally using lab-developed prototypes. [ABSTRACT FROM AUTHOR]

Impedance source inverters (ISIs) are gaining attention due to features such as single-stage conversion, buck-boost capability, and inherent shoot-through protection. To maintain the required ac output voltage, typically ISIs are operated at a higher dc-link voltage due to constrained modulation index. This also increases voltage stress across capacitors and switches of the converter. This voltage stress is approximately double compared to that of voltage source inverter with preboost stage (Boost-VSI). To mitigate this problem, a new pulsewidth modulation (PWM) scheme for the active-front-end based ISIs (AFE-ISIs) is proposed. The proposed scheme enables the ISIs to produce high ac gain with lower voltage stress across the capacitor and switches. In other words, the proposed scheme blends the advantages of Boost-VSI into ISIs. With the new PWM scheme, there are also reductions in output voltage total harmonic distortion, switching frequency ripple in the inductor current, and power loss in the converter. A prototype of the current-fed switched inverter, an AFE-ISI, is designed, and the proposed PWM scheme is implemented. Experimental results obtained are in accordance with the proposed theory and show that the voltage stress has reduced from 325 V to 203 V for an ac output of 110 V. [ABSTRACT FROM AUTHOR]