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A surface potential based compact model for two-dimensional field effect transistors (2D-FETs) is proposed to incorporate the structural disorders induced transition behaviors among variable range hopping (VRH), nearest neighbor hopping (NNH), and band-like transport in most 2D materials. These functions coupled with effective transport energy and multiple trapping and releasing theory enable our developed model to predict the temperature and carrier density dependent current characteristics. Its validity is confirmed by the experimental results such as the metal insulator transition (MIT) in transition metal dichalcogenides and VRH-NNH transition in black phosphorus nanoribbon. Based on this model, the band-tail effects on the crossover gate voltage of MIT behavior are quantitatively investigated. It is found that the transition behavior is closely related to the distribution of the band-tail states. Furthermore, this model is implemented in Verilog-A for circuit-level prediction and evaluation of 2D-FETs to provide deeper insight into the relationship between material properties, device physics, and circuit performances. [ABSTRACT FROM AUTHOR]

The analog resistive switching (RS) characteristics in 2-D polycrystalline (poly-) molybdenum disulfide (MoS2) field-effect transistors (FETs) enable new electronic devices capable of emulating biological synaptic behaviors. In 2-D poly-materials, grain boundary (GB)-induced trap states are of major significance to RS behaviors. However, there is still a lack of appropriate compact models that capture accurate physical mechanisms. Therefore, we developed a surface potential-based compact model, based on the theories of the GB energy barrier and space charge limited current (SCLC). By calibrating to experimental data of MoS2, the physical parameters are extracted, and the model explains the scaling behaviors of channel lengths and grain sizes. Due to the electric-field-induced defect redistribution, the energy barrier modulation at a single-GB (e.g., intersecting GB) quantitatively matches the reported experiments. Moreover, the possible SCLC-based RS behavior is also investigated. Furthermore, we have optimized the set/reset process and simulated the postsynaptic current (PSC) with a tunable potentiation (or depression) process, and then the gate voltage dependence and statistical effects on RS and PSC have been investigated. Thus, this model provides important devices physics insights of 2-D poly-materials and it guides device design, fabrication, and material engineering, to meet the requirements of the future neuromorphic computing application. [ABSTRACT FROM AUTHOR]

An improved simulation scheme for investigating the performance of nanoscale FETs is developed in this paper. The total current of the MOSFET consists of two main components: thermionic current above the top of barrier of the channel calculated by ballistic approach and tunneling current computed by Wentzel–Kramer–Brillouoin approximation based on a full-complex-band structure. Furthermore, to get atomic-position-based potential profile in the nanoscale device, we self-consistently solve atomic charges and potentials in the real space along and transverse in the transport direction. The device performance calculated with this model shows excellent agreement with that obtained using non-equilibrium Green’s function solver (full quantum mechanism) but by using only one-tenth of the simulation resource. Moreover, special characteristics of insulating materials integrated with advanced device structures can also be incorporated in this Poisson solver. An example based on the negative capacitance MOSFET is examined with this model, and it shows significantly improved performance than conventional MOSFET. [ABSTRACT FROM PUBLISHER]

A simple two step wet etch approach to fabricate nanowires (NWs) with a tapered source/drain (S/D) architecture is presented. Based on the unique NW architecture, gate-all-around junctionless NW FETs with sub-15-nm channel length ( $L_{{\mathrm{CH}}}$ ), NW height ( $H_{{\mathrm{NW}}}$ ), and NW width ( $W_{{\mathrm{NW}}}$ ) were realized. Despite having a large equivalent oxide thickness of $\sim 4.5$ nm, high extrinsic transconductance ( $G_{{m,{\mathrm{ ext}}}}) of 820 \mu \textS/\mu \textm was achieved at V\mathrm{ D} of 0.5 V. Due to the unique tapered S/D structure, the device realized in this paper achieved S/D series resistance ( R\mathrm {SD} ) of 275 \Omega \cdot \mu \mathrm m , which is one of the lowest among the reported 3-D InGaAs MOSFETs. [ABSTRACT FROM PUBLISHER]