Search

The method for modeling switching converters plays a key role in real-time simulators. Associate discrete circuit (ADC) modeling technique is a commonly used method for modeling the switching converter. However, the optimal selection of the ADC-based switch model parameters has great importance in the accuracy of the real-time simulator. In this paper, the design of a real-time simulator for a switching power converter has been done, in which a novel method for detecting optimum values of the switch model parameters has been expressed. Particle swarm optimization (PSO) algorithm is used to find these optimum values using state-space analysis of the modeled circuit in the z-domain. The modified nodal analysis (MNA) method solves the real-time model at each simulation time-step. Case studies are a single-phase 5-level Cascaded H-Bridge (CHB), three-phase 9-level CHB inverter, and a Transmission line. Field-programmable gate array (FPGA) has been used as a platform for implementing the real-time simulator. Experimental result of the real-time simulator of the 5-level CHB inverter on a SPARTAN-6 FPGA and its comparison with the result of a prototype of a 5-level CHB inverter confirms not only the performance of the real-time simulator, but also the effectiveness of the proposed method for confirming the real-time simulator accuracy. [ABSTRACT FROM AUTHOR]

This paper addresses the real-time optimization problem of the message-chain structure to maximize the throughput in data communications based on half-duplex command-response protocols. This paper proposes a new variant of the particle swarm optimization (PSO) algorithm to resolve real-time optimization, which is implemented on field programmable gate arrays (FPGA) to be performed faster in parallel and to avoid the delays caused by other tasks on a central processing unit. The proposed method was verified by finding the optimal message-chain structure much faster than the original PSO, as well as reliably with different system and algorithm parameters. [ABSTRACT FROM AUTHOR]

This paper introduces hybrid iterative algorithms that combine Particle Swarm Optimization (PSO) and Simulated Annealing (SA) algorithms for Field Programmable Gate Array (FPGA) placement by considering adaptive inertia weight and local minima avoidance. The algorithms target to optimize the wire-length of the nets, run time and critical path delay in the placement of logic blocks. Using the adaptive inertia weight parameter and local minima avoidance, the hybrid PSO-SA algorithm is modified to Time-varying PSO-SA (TPSO-SA) and Modified PSO-SA (MPSO-SA) algorithm, respectively. These different hybrid PSO-SA algorithms are checked for efficiency by comparing with the Versatile Place and Route (VPR) algorithm of the Verilog to Routing (VTR) tool using Microelectronics Centre of North Carolina (MCNC) benchmark circuits. The hybrid PSO-SA algorithms give 5–37% better results for wire-length cost and 20–58% reduction in runtime compared to the VPR placement algorithm on different benchmark circuits. Critical path delay is also taken into consideration. [ABSTRACT FROM AUTHOR]

In this study, field-programmable gate array (FPGA)-based hardware implementation of the wavelet neural network (WNN) training using particle swarm optimization (PSO) and improved particle swarm optimization (iPSO) algorithms are presented. The WNN architecture and wavelet activation function approach that is proper for the hardware implementation are suggested in the study. Using the suggested architecture and training algorithms, test operations are implemented on two different dynamic system recognition problems. From the test results obtained, it is observed that WNN architecture generalizes well and the activation function suggested has approximately the same success rate with the wavelet function defined in the literature. In the FPGA-based implementation, IEEE 754 floating-point number format is used. Experimental tests are done on Xilinx Artix 7 xc7a100t-1csg324 using ISE Webpack 14.7 program. [ABSTRACT FROM AUTHOR]