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To realize the complementary circuit on the GaN-on-Si platform, an investigation of p-channel heterostructure field-effect transistors (p-HFETs) is necessary. In this study, an analytical model for the estimation of the threshold voltage (${V}_{\text {TH}}$) for GaN-based p-HFETs was developed. In this model, the impact of polarization charges at different interfaces, the influence of interface charges at oxide/GaN interface, as well as the out-diffusion effect of Mg dopant in the p-GaN layer were all taken into consideration for systematic exploration. Herein, GaN-based p-HFETs were fabricated to verify the relationship between the ${V}_{\text {TH}}$ and the thickness of the GaN channel layer by using the proposed model. The ${V}_{\text {TH}}$ model was further confirmed through TCAD simulations. The influences of the thickness of oxide layer, Mg doping concentration in p-GaN layer, and the Al mole fraction of AlxGa $_{{1}-{x}}\text{N}$ layer on ${V}_{\text {TH}}$ were also discussed in detail. The model serves as more accurate guidance for the optimization of such p-HFETs design and complementary circuits. [ABSTRACT FROM AUTHOR]

The gate and drain bias dependence of hot electron-induced degradation in GaN-based metal–insulator–semiconductor high electron mobility transistors (MIS-HEMTs) was investigated in this work. Devices exhibit an abnormal increase in peak transconductance (${G}_{m}$ ,max) during hot carrier stress (HCS) and a partially quick recovery of that after removing the electrical stress. A physical model is proposed to explain the abnormal electrical characteristics caused by HCS. By using density functional theory (DFT), we calculated the energy for electrons to dehydrogenate preexisting [NGaH3]−1 complexes in GaN layer during stress. The dehydrogenation of defects affects the Gm,max of devices. Meanwhile, the neutralization of donor traps in AlGaN barrier layer also plays a significant role in the increase of Gm,max and the detrapping effect of electrons from these traps after removing the electrical stress accounts for the partially quick recovery of ${G}_{m, \text{max}}$. [ABSTRACT FROM AUTHOR]

In this article, we report on the effective transconductance (gm) and gain linearity improvement of submicrometer gate AlN-barrier-based transistors using GaN/InGaN coupling-channel structures. The fabricated AlN/GaN/InGaN coupling-channel high electron mobility transistor (CC-HEMT) showed flat gm profile, greatly reduced gm derivatives, and constant dynamic source resistance compared with an AlN/GaN HEMT using the same fabrication process. The highest extrinsic current gain cutoff frequency (ƒT) of 55 GHz and the maximum oscillation frequency (ƒmax) of 80 GHz were obtained for 0.15- μm gate-length transistors, both of which remain constant values across wide input voltage (VGS) of 4 V. Moreover, a significant theoretical OIP3 value boost by 7.1 dB has been observed using the CC-HEMT as compared to the AlN/GaN HEMT. The superior linearity performance of the CC-HEMT can be attributed to the strong channel-to-channel coupling effect. The drain bias-dependence of gm, ƒT, and ƒmax versus VGS profiles illustrate that the linearity characteristics of the CC-HEMT greatly improve with an increase in VDS. These results demonstrate the AlN/GaN/InGaN material system as a viable platform for high frequency requiring high-linearity applications. [ABSTRACT FROM AUTHOR]

In order to further improve the electrical characteristics of AlGaN-buffer devices, we propose a new in situ SiN/AlGaN-sandwich-barrier (SWB)/GaN/Al0.05GaN high-electron mobility transistors (HEMTs). The dc, channel temperature, and RF temperature of the proposed AlGaN-buffer devices have been systematically studied and analyzed. The SWB structure can effectively reduce the peak value of the electric field, thus effectively reducing the self-heating effect and improving the breakdown characteristics. Through the channel temperature extraction method of pulsed IV and TCAD thermal simulation, the channel temperature of devices with different barrier structures is compared and analyzed, which proves that SWB structure can effectively reduce the channel temperature of devices. Due to the more obvious potential modulation effect between gate and drain, the ƒmax of device can improve more effectively with the increase of drain voltage. In addition, load-pull measurement at 10 GHz revealed that a saturated power density increased from 7.3 to 8.4 W/mm and an associated PAE increased from 24.9% to 29.4%. [ABSTRACT FROM AUTHOR]