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Deterministic lateral displacement (DLD) is a passive separation method that separates particles by hydrodynamic size. This label-free method is a promising technique for cell separation because of its high size resolution and insensitivity to flow rate. Development of capillary-driven microfluidic technologies allows microfluidic devices to be operated without any external power for fluid pumping, lowering their total cost and complexity. Herein, we develop and test a DLD-based particle and cell sorting method that is driven entirely by capillary pressure. We show microchip self-filling, flow focusing, flow stability, and capture of separated particles. We achieve separation efficiency of 92% for particle–particle separation and more than 99% efficiency for cell–particle separation. The high performance of driven flow and separation along with simplicity of the operation and setup make it a valuable candidate for point-of-care devices. [ABSTRACT FROM AUTHOR]

Due to the increasing size of integrated circuits (ICs), their design and optimization phases (i.e., computer-aided design, CAD) grow increasingly complex. At design time, a large design space needs to be explored to find an implementation that fulfills all specifications and then optimizes metrics like energy, area, delay, reliability, etc. At run time, a large configuration space needs to be searched to find the best set of parameters (e.g., voltage/frequency) to further optimize the system. Both spaces are infeasible for exhaustive search typically leading to heuristic optimization algorithms that find some tradeoff between design quality and computational overhead. Machine learning (ML) can build powerful models that have successfully been employed in related domains. In this survey, we categorize how ML may be used and is used for design-time and run-time optimization and exploration strategies of ICs. A metastudy of published techniques unveils areas in CAD that are well explored and underexplored with ML, as well as trends in the employed ML algorithms. We present a comprehensive categorization and summary of the state of the art on ML for CAD. Finally, we summarize the remaining challenges and promising open research directions. [ABSTRACT FROM AUTHOR]

Background: Microfluidic chip detection technology is considered a potent tool for many bioanalytic applications. Rapid detection of foodborne pathogens in the early stages is imperative to prevent the outbreak of foodborne diseases, known as a severe threat to human health. Conventional bacterial culture methods for detecting foodborne pathogens are time-consuming, laborious, and lacking in pathogen diagnosis. To overcome this problem, we have created an embedded paper-based microchip based on isothermal loop amplification (LAMP), which can rapidly and sensitively detect foodborne pathogens. Results: We embed paper impregnated with LAMP reagent and specific primers in multiple reaction chambers of the microchip. The solution containing the target pathogen was injected into the center chamber and uniformly distributed into the reaction chamber by centrifugal force. The purified DNA of Escherichia coli O157:H7, Salmonella spp., Staphylococcus aureus, and Vibrio parahaemolyticus has been successfully amplified and directly detected on the microchip. The E. coli O157:H7 DNA was identified as low as 0.0134 ng μL− 1. Besides, the potential of this microchip in point-of-care testing was further tested by combining the on-chip sample purification module and using milk spiked with Salmonella spp.. The pyrolyzed milk sample was filtered through a polydopamine-coated paper embedded in the inside of the sample chamber. It was transported to the reaction chamber by centrifugal force for LAMP amplification. Then direct chip detection was performed in the reaction chamber embedded with calcein-soaked paper. The detection limit of Salmonella spp. in the sample measured by the microchip was approximately 12 CFU mL− 1. Conclusion: The paper embedded LAMP microchip offers inexpensive, user-friendly, and highly selective pathogen detection capabilities. It is expected to have great potential as a quick, efficient, and cost-effective solution for future foodborne pathogen detection. [ABSTRACT FROM AUTHOR]

Plasmonic metal nanostructures generate vivid colors with high spatial resolution. Active control of plasmonic pixels by electrical means, which is compatible with integrated circuit technologies, is a promising technique for dynamic full color reflective display. However, the development of electrical plasmonic display is still limited by the difficulties in cost‐effective construction of active plasmonic pixels over large areas. This study demonstrates the achievement of electrical plasmonic display in full color by electrophoretic movement control of plasmonic noble metal nanocrystals in an organic electrolyte solvent. The persistent issues of nanoparticle aggregation and irreversible deposition in electrophoresis are addressed through appropriate surface modifications of the plasmonic nanocrystals, enabling them as advantageous nanoscale colorful pigments with long‐term durability. A weak electric field therefore allows color display with high contrast, high saturation, and electrical reconfigurability. The ink containing plasmonic pigments is further assembled into microfluidic chips to display different characters. The strategy will pave the way towards the development of plasmonic electronic paper in full color. [ABSTRACT FROM AUTHOR]

Highlights • An integrated sealed-type paper-based platform is proposed for SO 2 detection. • A filter paper is coated with acid-base indicator and inserted in a PET-based microchip. • SO 2 concentrations of 25 commercial food samples are measured. • The measurement results deviate by no more than 3.82% versus official method. Abstract A convenient assay platform comprising a PET/paper chip (PP-chip) and a smart analytical device is developed for detection of sulphur dioxide (SO 2) concentration. In the presented approach, the distilled SO 2 solution is dropped onto the detection region of the PP-chip and undergoes a reaction with an acid-based reagent. The resulting color variation is analyzed through a high-resolution camera (CMOS) and the reacted image is processed by a RGB (red, green and blue) analytical app installed on a smartphone. Results show that the known SO 2 concentrations ranging from 10 to 300 ppm indicate that the high linear relationship (R2 = 0.9981) between the (R (red) + G (green) − B (blue)) value and SO 2 concentration. Moreover, a high measurement resolution is equal to 1.45 ppm/a.u. The presented assay platform was proved to detect the SO 2 concentrations of twenty-five practical food samples. Compared with the developed assay platform and certified inspection technique, the deviation of SO 2 measurement does not exceed 3.82%. It was satisfactory to apply this developed assay platform to analyze the SO 2 concentration in the practical samples. [ABSTRACT FROM AUTHOR]

Paper chip is an efficient and inexpensive device for pesticide residues detection. However, the reasons of detection error are not clear, which is the main problem to hinder the development of pesticide residues detection. This paper focuses on error analysis for pesticide detection performed on paper-based microfluidic chip devices, which test every possible factor to build the mathematical models for detection error. In the result, double-channel structure is selected as the optimal chip structure to reduce detection error effectively. The wavelength of 599.753 nm is chosen since it is the most sensitive detection wavelength to the variation of pesticide concentration. At last, the mathematical models of detection error for detection temperature and prepared time are concluded. This research lays a theory foundation on accurate pesticide residues detection based on paper-based microfluidic chip devices. [ABSTRACT FROM AUTHOR]

[Display omitted] • A method for fabricating integrated multi-electrodes inside a single sheet of paper. • A paper used in two dimensions used as a three-dimensional scaffold. • The control of the equivalent circuit without changing external circuits and wires. Paper is an excellent substrate for flexible devices due to its various advantages such as flexibility, porosity, lightness, and thinness. Its inherent characteristics can be also exploited to overcome the limitations of conventional substrates, such as weak adhesion and large mass densities. Here, we propose a method for fabricating vertically integrated multi-electrodes within only a single sheet of paper. Despite the randomly distributed fibrous networks in a paper, the multi-layered electrodes were uniformly formed and completely separated by applying a removable hydrophobic wax barrier confinement inside a single sheet of paper. The integrated multi-layer electrodes inside a single sheet of paper mean that conventional two-dimensional planes can be used as three-dimensional scaffolds. The highly integrated electrodes and circuit systems are located within only a sheet of paper, making a new possibility to design maximizing the energy storage performance, integrated circuit systems, and significantly decreasing the thickness of the system without external complex structure. In consequence, this unique platform can circumvent most of the fabrication challenges related to two-dimensional energy storage sheets. [ABSTRACT FROM AUTHOR]

All-inkjet-printing of transistors has received much attention for low cost and flexible integrated circuits. However, most flexible field-effect transistors (FETs) based on the emerging two-dimensional materials suffer from the high cost of substrate and electrode materials. The requirements for high-temperature synthesis and precise control in processing add another layer of complexity. To overcome these issues, low-cost flexible paper-based MoS2 FETs were fabricated by inkjet printing of MoS2 channel materials on paper. Additionally, we proposed and achieved the mask-less and low-temperature formation of source and drain electrodes on paper using in-situ selective-area copper reduction. A low sub-threshold swing of 80 mV/dec, high on/off ratio of 105, and very high turn-on current (Ion) of 200 μA of the paper-based flexible MoS2 FETs were demonstrated using the proposed low-cost and facile all-inkjet-printing technique. The all-inkjet-printing technique assisted by in-situ copper reduction opens new opportunities for low-cost and batch fabrication of paper-based electronic devices in ambient conditions. [ABSTRACT FROM AUTHOR]

This Special Issue of the IEEE Journal of Solid-State Circuits is dedicated to a set of the best papers selected from the 2018 IEEE International Solid-State Circuits Conference (ISSCC) that took place February 11–15, 2018, in San Francisco, CA, USA. This issue covers papers from the Analog, Power Management, Data Converters, RF, and Wireless committees. [ABSTRACT FROM AUTHOR]

Among recent technological advances, microfluidic biochips have been leading a prominent solution for healthcare and miniaturized bio-laboratories with the assurance of high sensitivity and reconfigurability. On increasing more unreliable communication networks day-by-day, technological shifts in the fields of communication and security are now converging. In today's cyber threat landscape, these microfluidic biochips are ripe targets of powerful cyber-attacks from different hackers or cyber-criminals. Hence, securing such systems is of paramount importance. This paper presents the security aspects of digital microfluidic biochip layout to protect the confidentiality of layout data from unscrupulous people and man-in-the-middle attacks. We propose an authentication mechanism with an error control mechanism that provides reliability, authentication, trustworthy and safety for both storage and communication of GDS, i.e., Graphical Design System, file generally used for digital microfluidic biochip layouts. Simulation results articulate the efficacy of the proposed security model without the overhead of the bioprotocol completion time. The proposed scheme, which used AES as an encryption algorithm with a 256-bit encryption key, has also shown a speedup of 6.0 (with 85% efficiency) faster than the prior efficient scheme. We hope to develop a secure layout design flow for biochips to achieve better resistance to any attack. [ABSTRACT FROM AUTHOR]

This paper proposes a digital delay locked loop (DLL) with a monotonic delay line (DL). This DLL adopts the calibration mode to reduce the non‐monotonic effects for the coarse‐tuning delay line (CTDL) and the fine‐tuning delay line (FTDL). The calibration mode detects the delay time of the delay unit, the timing resolution of CTDL, to adjust the delay range of the FTDL. Thus, the calibration mode can limit the overlap range of the delay time between the CTDL and the FTDL. The proposed DLL was implemented using a 0.18‐μm CMOS process, and the RMS and the peak‐to‐peak jitters of the DLL were 0.21% and 1.72%, respectively, at 560 MHz. [ABSTRACT FROM AUTHOR]

Plastic microfluidic devices with embedded chitosan-modified Fusion 5 filter paper (unmodified one purchased from GE Healthcare) have been successfully developed for DNA extraction and concentration, utilizing two different mechanisms for DNA capture: the physical entanglement of long-chain DNA molecules with the fiber matrix of the filter paper and the electrostatic adsorption of DNA to the chitosan-modified filter fibers. This new method not only provided a high DNA extraction efficiency at a pH of 5 by synergistically combining these two capture mechanisms together, but also resisted the elution of DNA from filters at a pH > 8 due to the entanglement of DNA with fibers. As a result, PCR buffers can be directly loaded into the extraction chamber for "in situ PCR", in which the captured DNA were used for downstream analysis without any loss. We demonstrated that the capture efficiencies of a 3-mm-diameter filter disc in a microchip were 98% and 95% for K562 human genomic DNA and bacteriophage λ -DNA, respectively. The washes with DI water, PCR mixture, and TE buffer cannot elute the captured DNA. In addition, the filter disc can enrich 62% of λ -DNA from a diluted sample (0.05 ng/µL), providing a concentration factor more than 30-fold. Finally, a microdevice with a simple two-chamber structure was developed for on-chip cell lysis, DNA extraction, and 15-plex short tandem repeat amplification from blood. This DNA extraction coupled with "in situ PCR" has great potential to be utilized in fully integrated microsystems for rapid, near-patient nucleic acid testing. [ABSTRACT FROM AUTHOR]

Traditional diagnostic tests for chronic diseases are expensive and require a specialized laboratory, therefore limiting their use for point-of-care (PoC) testing. To address this gap, we developed a method for rapid and low-cost C-reactive protein (CRP) detection from blood by integrating a paper-based microfluidic immunoassay with a smartphone (CRP-Chip). We chose CRP for this initial development because it is a strong biomarker of prognosis in chronic heart and kidney disease. The microfluidic immunoassay is realized by lateral flow and gold nanoparticle-based colorimetric detection of the target protein. The test image signal is acquired and analyzed using a commercial smartphone with an attached microlens and a 3D-printed chip-phone interface. The CRP-Chip was validated for detecting CRP in blood samples from chronic kidney disease patients and healthy subjects. The linear detection range of the CRP-Chip is up to 2 µg/mL and the detection limit is 54 ng/mL. The CRP-Chip test result yields high reproducibility and is consistent with the standard ELISA kit. A single CRP-Chip can perform the test in triplicate on a single chip within 15 min for less than 50 US cents of material cost. This CRP-Chip with attractive features of low-cost, fast test speed, and integrated easy operation with smartphones has the potential to enable future clinical PoC chronic disease diagnosis and risk stratification by parallel measurements of a panel of protein biomarkers. [ABSTRACT FROM AUTHOR]

This paper proposes a visual management scheme of medical things with a color-change radio frequency identification (RFID) tag. The color-change RFID tag employs a specific RFID tag integrated circuit (IC) and a laminated pH-indicating paper. The IC has energy harvesting and switched ground functions, which enable it to generate electricity to the laminated pH-indicating paper. This phenomenon causes electrolysis of NaCl solution absorbed in the laminated pH-indicating paper. Electrolysis generates alkaline matter to change the color of the pH-indicating paper. This paper gives a new and sensitive structure of the laminated pH-indicating paper. The proposed advanced color-change RFID tag with new laminated pH-indicating paper succeeds in changing its color noticeably at a 1 m distance using an RFID reader radiating 1 W radio waves. The color change was observed 3–5 s after starting radio wave irradiation. The results of this experiment also confirm that the changed color can be held for over 24 h. Furthermore, two demonstrations of the visual management system of medical things (patient clothes and sanitizers) are presented. [ABSTRACT FROM AUTHOR]

This special issue contains papers obtained through open call-for-papers as well as from the selected extended versions of the papers presented in the 4th International Conference "2021 Devices for Integrated Circuit (DevIC)", held at Kalyani Government Engineering College from May 19-20, 2021. This special issue publishes a collection of papers that were submitted to the Journal of Materials Science: Materials in Electronics on the theme of experimental electronic and optical materials for nano-dimensional device applications. [Extracted from the article]

With the development of electronic technology, semiconductor memory is gradually shifting toward smaller area with less power consumption. SOT-MRAM is one of the competitive substitutes for DRAM and SRAM due to its superior endurance and switching speed. In contrast to STT-MRAM, the separation of read and write routes allows SOT-MRAM to have a lower error rate and higher lifetime, but this comes at the expense of the memory density. In recent years, vertical integrated circuits have relied on TSV to complete 3D stacking to ease the pressure of Moore's Law on scaling circuits. SOT-MRAM can take advantage of 3D stacking to reduce power and latency. More importantly, the density of SOT-MRAM can be improved at the same time. In the paper, simulation is conducted based on DESTINY, with the TSV model supplemented to NVSIM to evaluate the performance of MRAM 3D structures. The 3D SOT-MRAM structure in DESTINY can be implemented with a bus layer and interconnect structure between layers, which greatly reduces the expense of area. However, the 3D structure requires a more complex interconnect structure to truly meet the requirements of high density. For this reason, 3D model of unit interconnection using TSV is presented in the paper. Memory has several components, of which the memory array is the one with the largest area share. This paper explores the spatial structure of the array and proposes a new model which allows more complex interconnect structures to be accomplished on the same area. [ABSTRACT FROM AUTHOR]

Diagnosing multi-stage diseases typically requires doctors to consider multiple data sources, including clinical symptoms, physical signs, biochemical test results, imaging findings, pathological examination data, and even genetic data. When applying machine learning modeling to predict and diagnose multi-stage diseases, several challenges need to be addressed. Firstly, the model needs to handle multimodal data, as the data used by doctors for diagnosis includes image data, natural language data, and structured data. Secondly, privacy of patients' data needs to be protected, as these data contain the most sensitive and private information. Lastly, considering the practicality of the model, the computational requirements should not be too high. To address these challenges, this paper proposes a privacy-preserving federated deep learning diagnostic method for multi-stage diseases. This method improves the forward and backward propagation processes of deep neural network modeling algorithms and introduces a homomorphic encryption step to design a federated modeling algorithm without the need for an arbiter. It also utilizes dedicated integrated circuits to implement the hardware Paillier algorithm, providing accelerated support for homomorphic encryption in modeling. Finally, this paper designs and conducts experiments to evaluate the proposed solution. The experimental results show that in privacy-preserving federated deep learning diagnostic modeling, the method in this paper achieves the same modeling performance as ordinary modeling without privacy protection, and has higher modeling speed compared to similar algorithms. [ABSTRACT FROM AUTHOR]

This paper reports an industry standard monolithic 555-timer circuit designed and fabricated in the in-house silicon carbide (SiC) low-voltage bipolar technology. This paper demonstrates the 555-timer integrated circuits (ICs) characterization in both astable and monostable modes of operation, with a supply voltage of 15 V over the wide temperature range of 25 °C–500 °C. Nonmonotonic temperature dependence was observed for the 555-timer IC frequency, rise time, fall-time, and power dissipation. [ABSTRACT FROM AUTHOR]

A microfluidic colorimetric detection (MCD) platform consisting of a sliding hybrid PMMA/paper microchip and a smart analysis system is proposed for the convenient, low-cost and rapid analysis of human urine and whole blood samples. The sliding PMMA/paper microchip comprises a PMMA microfluidic chip for sample injection and transportation, a paper strip for sample filtration (urine) or separation (blood), and a sealed paper-chip detection zone for sample reaction and detection. In the proposed device, the paper-chip is coated with bicinchoninic acid (BCA) and biuret reagent and is then assembled into the PMMA microchip and packaged in aluminum housing. In the detection process, the PMMA/paper microchip is slid partially out of the housing, and 2 μL of sample (urine or whole blood) is dripped onto the sample injection zone. The chip is then slid back into the housing and the sample is filtered/separated by the paper strip and transferred under the effects of capillary action to the sealed paper-chip detection zone. The housing is inserted into the color analysis system and heated at 45 °C for 5 min to produce a purple-colored reaction complex. The complex is imaged using a CCD camera and the RGB color intensity of the image is then analyzed using a smartphone to determine the total protein (TP) concentration of the sample. The effectiveness of the proposed method is demonstrated using TP control samples with known concentrations in the range of 0.03–5.0 g/dL. The detection results obtained for 50 human urine samples obtained from random volunteers are shown to be consistent with those obtained from a conventional hospital analysis system (R2 = 0.992). Moreover, the detection results obtained for the albumin (ALB) and creatine (CRE) concentrations of 50 whole blood samples are also shown to be in good agreement with the results obtained from the hospital analysis system (R2 = 0.982 and 0.988, respectively). [Display omitted] • A MCD platform is presented for detection of urine and whole blood samples. • The platform comprises a sliding hybrid microchip and an intelligent analysis system. • The hybrid microchip has the functions of filtering urine and separating whole blood. • The hybrid microchip drives the fluid by capillary force without external driving force. • The platform can perform the detection of urine TP, whole blood ALB and CRE concentration. [ABSTRACT FROM AUTHOR]

Two-dimensional (2D) materials represent an emerging technology for transistor electronics in view of their attractive electrical and mechanical properties. This work investigates molybdenum disulfide (MoS 2) based field-effect transistors (FETs) fabricated on paper substrate for designing both digital and analog circuits, such as inverter, current mirror, and Physical Unclonable Function (PUF) bitcell. Electrical measurements of fabricated devices are exploited to setup a look-up-table (LUT)-based Verilog-A model to be integrated in a commercial circuit simulator. Obtained results prove the potential of paper-based MoS 2 FETs as building blocks of next-generation integrated circuits for a wide range of practical applications. [ABSTRACT FROM AUTHOR]

Origami, an ancient form of papercraft, provides a way to develop functional structures for engineering applications. In this paper, we report an approach to design and manufacture a stretchable circuit board (SCB) with origami structures. The benefits of developable, flat-foldable, and rigid-foldable origami-based structures as SCBs are discussed, and a representative structure, Miura fold (or Miura-ori), is chosen to be investigated. Under the constraints induced by the mounted components' dimensions, the Miura-ori structures for specific applications can be defined. We propose three methods for better fabrication, including direct folding, stiffness modification, and kirigami enhancement, to improve a planar sheet's foldability. A wearable ECG (electrocardiogram) system based on MO-SCB (Miura-ori enabled SCB) technology is built, and the stretchable portion is made of commercial FPCBs (flexible printed circuit board), providing desired stretchability and reliability. The proposed technology routine is compatible with industrial production and may pave the application of stretchable electronics. [ABSTRACT FROM AUTHOR]

The top‐gate 4.5‐nm‐thick SnO2 nanosheet nTFT has the high 136 cm2/Vs field‐effect mobility (μFE), sharp 1.5×108 on‐current/off‐current (ION/IOFF), and fast turn‐on subthreshold slope (SS) of 108 mV/decade. The top‐gate 7‐nm‐thick nanosheet SnO pTFT has a high μFE of 4.4 cm2/Vs, large ION/IOFF of 1.2×105, and SS of 526 mV/decade. These CTFTs will enable the system‐on‐panel (SoP) and Monolithic Three‐Dimensional (3D) Integrated Circuit (IC). [ABSTRACT FROM AUTHOR]

Air‐stable semiconducting inks suitable for complementary logic are key to create low‐power printed integrated circuits (ICs). High‐performance printable electronic inks with 2D materials have the potential to enable the next generation of high performance low‐cost printed digital electronics. Here, the authors demonstrate air‐stable, low voltage (<5 V) operation of inkjet‐printed n‐type molybdenum disulfide (MoS2), and p‐type indacenodithiophene‐co‐benzothiadiazole (IDT‐BT) field‐effect transistors (FETs), estimating an average switching time of τMoS2 ≈ 4.1 μs for the MoS2 FETs. They achieve this by engineering high‐quality MoS2 and air‐stable IDT‐BT inks suitable for inkjet‐printing complementary pairs of n‐type MoS2 and p‐type IDT‐BT FETs. They then integrate MoS2 and IDT‐BT FETs to realize inkjet‐printed complementary logic inverters with a voltage gain |Av| ≈ 4 when in resistive load configuration and |Av| ≈ 1.4 in complementary configuration. These results represent a key enabling step towards ubiquitous long‐term stable, low‐cost printed digital ICs. [ABSTRACT FROM AUTHOR]

The limits of chip technology are constantly being pushed with the continuous development of integrated circuit manufacturing processes and equipment. Currently, chips contain several billion, and even tens of billions, of transistors, making chip testing increasingly challenging. The verification of very large-scale integrated circuits (VLSI) requires testing on specialized automatic test equipment (ATE), but their cost and size significantly limit their applicability. The current FPGA-based ATE is limited in its scalability and support for few test channels and short test vector lengths. As a result, it is only suitable for testing specific chips in small-scale circuits and cannot be used to test VLSI. This paper proposes a low-cost hardware and software solution for testing digital integrated circuits based on design for testability (DFT) on chips, which enables the functional and performance test of the chip. The solution proposed can effectively use the resources within the FPGA to provide additional test channels. Furthermore, the round-robin data transmission mode can also support test vectors of any length and it can satisfy different types of chip test projects through the dynamic configuration of each test channel. The experiment successfully tested a digital signal processor (DSP) chip with 72 scan test pins (theoretically supporting 160 test pins). Compared to our previous work, the work in this paper increases the number of test channels by four times while reducing resource utilization per channel by 37.5%, demonstrating good scalability and versatility. [ABSTRACT FROM AUTHOR]

With the rapid development of semiconductor technology, the reduction in device operating voltage and threshold voltage has made integrated circuits more susceptible to the effects of particle radiation. Moreover, as process sizes decrease, the impact of charge sharing effects becomes increasingly severe, with soft errors caused by single event effects becoming one of the main causes of circuit failures. Therefore, the study of sensitivity evaluation methods for integrated circuits is of great significance for promoting the optimization of integrated circuit design, improving single event effect experimental methods, and enhancing the irradiation reliability of integrated circuits. In this paper, we first established a device model for the charge sharing effect and simulated it under reasonable conditions. Based on the simulation results, we then built a neural network model to predict the charge amounts in primary and secondary devices. We also propose a comprehensive automated method for calculating soft errors in unit circuits and validated it through TCAD simulations, achieving an error margin of 2.8–4.3%. This demonstrated the accuracy and effectiveness of the method we propose. [ABSTRACT FROM AUTHOR]

This Special Issue of the IEEE Journal of Solid-State Circuits highlights some of the best papers presented at the 32nd Symposium on VLSI Circuits, held on June 18–22, 2018, at the Hilton Hawaiian Village, Honolulu, HI, USA. Industry and university engineers from all over the world reported innovative new techniques and state-of-the-art results. Papers presented covered a broad range of topics important to VLSI circuit and system designers, including topics that are also important to integrated circuit technology developers. [ABSTRACT FROM AUTHOR]