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Even though virtual oscillator control (VOC)-based inverters do not communicate with each other, they need to make local measurements for control. The impact of tampering with these measured or sensed signals on the performance of a VOC-based inverter and synchronization of multiple such inverters is an important but open-ended issue. As such, this letter explores the impact of intentional side-channel noise intrusion (SNI) on the synchronization of VOC-based communication-free self-synchronizing inverters (CFSIs). Two different scenarios are investigated via experimental and analytical studies using a half-bridge neutral point clamped (NPC) single-phase CFSI. They address the impact of SNI on the ability of a CFSI to ensure a stable 60-Hz limit cycle and on the parallel operation of two such CFSIs to ensure synchronism to a common 60-Hz load frequency. [ABSTRACT FROM AUTHOR]

A series of novel externally reconfigurable power electronic modules (RPEMs) are invented to increase the flexibility of power modules and their application purposes. In this article, the concept of RPEMs, their switching arrangements, and power-module-based architectural design are demonstrated. An RPEM is then designed, analyzed through simulations, and compared with the conventional fixed-configuration power electronic modules. The sizes of the power modules and used power terminals are kept similar to avoid any differences in power loop inductance values solely due to various trace pad sizes. In addition, similar gate/source pads and signal pins are used for all of the designed power modules to have constant switching dynamics in all modules. The comparison results show that the internal parasitic inductance and performance are still comparable with the conventional modules despite having high configurability. The designed RPEM and a conventional full-bridge (FB) power module are fabricated and characterized. The experimental tests show that the difference between the overshoot voltages on both RPEM and FB power modules is less than 2%. Such flexibility without compromising the power module performance decreases the engineering time for designing different power modules for various power electronic converters; hence, the production speed can be improved while decreasing the overall module cost. [ABSTRACT FROM AUTHOR]

This article presents the design and demonstration of an all silicon carbide (SiC) 2×250 kW dual inverter for heavy-duty traction applications. Through the use of a formal electrothermal-control co-design approach, the maximum power density of the proposed inverter system is 60 kW/L, which is accomplished by. More specifically, to analyze the thermal performance of the inverter, a lumped thermal model is developed based on the characteristics of the power modules and the cold plate. To analyze the complicated interaction between the power losses and module junction temperatures, a closed-loop iterative estimation scheme is proposed to estimate the inverter power loss and module junction temperature. Based on the proposed thermal model and estimation scheme, a detailed optimization procedure on the selection of switching frequency and dc-link capacitor is presented to maximize power density. Furthermore, design optimization of the busbar was conducted to minimize the stray inductance, thus reducing the voltage overshoot during switching transients. Comprehensive experimental studies were performed on a physical converter prototype built based on the optimization results, which validate both the effectiveness of the presented design approach. [ABSTRACT FROM AUTHOR]

The silicon carbide (SiC) devices have faster switching speed than that of the conventional silicon (Si) devices, which however may cause excessive device voltage overshoot. Larger gate resistance can help to restrain the overshoot, it however slows down the switching speed and increases switching losses. There are other methods that can mitigate the voltage overshoot, e.g., using low-inductance busbars, adding snubber circuits, etc. In this article, the busbar design for a 250-kW SiC three-level T-type inverter is investigated. The current commutation loops (CCLs) are first analyzed using a single-phase equivalent circuit. Then the detailed busbar design methods, especially a 3-D busbar design concept, are proposed to select the optimal stacking order for the multilayer laminated busbar and to address constraints posed by the physical terminal arrangements of SiC modules and dc-link capacitors. The stray inductance in each CCL is extracted via a finite element analysis and validated on the actual inverter busbar prototypes using an impedance analyzer. To further minimize the busbar stray inductance, a hybrid busbar structure with printed circuit board based buffer circuit using high-frequency decoupling capacitors is designed and evaluated in this article. Finally, the effectiveness of the designed busbars as well as the buffer circuit are validated using experimental studies. [ABSTRACT FROM AUTHOR]

The cascaded H-bridge (CHB) inverter is one of the most attractive multilevel topologies for renewable energy applications. Due to the fact that CHB inverters employ a large number of components, they suffer from a higher probability of fault, which reduces the system reliability. A fault-tolerant operation for a CHB inverter is described in this article. New features ensure reliable and robust operation of the converter in the event of a fault. The proposed strategy uses an additional cross-coupled CHB (X-CHB) unit in companion with the existing CHB units to support the output voltage and ensure continuity of operation in the event of an open/short-circuit fault. The operation of the proposed X-CHB inverter is described in detail. Simulation and experimental verification of the proposed concept are demonstrated using a seven-level CHB. Both simulation and experimental results confirm the fault-tolerant operation of the X-CHB for a battery energy storage system in case of switch faults. [ABSTRACT FROM AUTHOR]