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Ferroelectric (FE) negative capacitance (NC) MOSFETs is investigated in depth with a full real-space atomic simulator. For the first time, Gibbs-free energy of the whole atomic system is employed to determine the appropriate operation region in polarization-electric-field (${P}$ – ${E}$) path of the FE layer for FE MOSFETs. With different FE thicknesses, the operation path of the FE layer in MOS structures can be hysteresis or hysteresis-free. For MOSFET structures, the operation path of FE layer will vary with different FE materials. With proper device parameters, the NC effect in FE layer can be obtained with minimum Gibbs-free energy of the MOS and MOSFET structures. The body factor, ${dV}_{G}/{d} \Psi _{S}$ , is obtained with the real-space structure to reflect the influence of the FE layer and optimize the device performance. With the FE layer of the same thickness, the NC-FET with longer channel has a larger body factor which causes the tradeoff between low tunneling current and small body factor. This tradeoff makes it difficult to improve the subthreshold swing by changing the gate length. In addition, the effect of floating metal layer between FE and SiO2 layers in NC-FETs is studied in detail with atomic level real-space analysis for different gate lengths. The metal layer has a stronger influence on the electric characteristics of NC-FETs with longer channel. [ABSTRACT FROM AUTHOR]

We report the ultimate performance of a double-gate ultrathin body (DG-UTB) FET employing materials from group IV, III-V, and 2-D materials based on International Technology Roadmap for Semiconductors (ITRS) projected specifications for high-performance (HP) and low-power (LP) technologies. The band structures of the channel materials were obtained using the sp ^3\textd^5\texts^\ast tight binding model and the first-principles density functional theory. The ballistic performance of FETs designed based on the ITRS specifications for 2018 and beyond was evaluated via the semiclassical ballistic transport model. The leakage current due to direct source-to-drain tunneling was calculated based on Wentzel–Kramers–Brillouin approximation. For nFET used in the HP technology, GaSb nFET has the best voltage scalability followed by Ge nFET in 2026. It was found that I\mathrm{\scriptscriptstyle ON} of InAs and In0.3 Ga0.7Sb nFETs is among the lowest, and they require larger power supply voltage ( V\mathrm{DD} ) among III-V semiconductors considered to achieve I\mathrm{\scriptscriptstyle ON} of silicon nFET. However, they show lower power delay product (PDP) due to their smaller electron effective mass, resulting in higher carrier velocity. Ge pFET offers the best voltage scalability for pFET used in the HP technology. For the voltage scalability assessment based on the requirements for the LP technology, MOSFETs based on Si offer better performance in terms of I\mathrm{\scriptscriptstyle ON} and PDP than MOSFETs based on 2-D materials. Among the 2-D materials studied, black phosphorus and silicane MOSFETs exhibit higher I\mathrm{\scriptscriptstyle ON} and better voltage scalability and PDP. [ABSTRACT FROM AUTHOR]

An improved simulation scheme for investigating the performance of nanoscale FETs is developed in this paper. The total current of the MOSFET consists of two main components: thermionic current above the top of barrier of the channel calculated by ballistic approach and tunneling current computed by Wentzel–Kramer–Brillouoin approximation based on a full-complex-band structure. Furthermore, to get atomic-position-based potential profile in the nanoscale device, we self-consistently solve atomic charges and potentials in the real space along and transverse in the transport direction. The device performance calculated with this model shows excellent agreement with that obtained using non-equilibrium Green’s function solver (full quantum mechanism) but by using only one-tenth of the simulation resource. Moreover, special characteristics of insulating materials integrated with advanced device structures can also be incorporated in this Poisson solver. An example based on the negative capacitance MOSFET is examined with this model, and it shows significantly improved performance than conventional MOSFET. [ABSTRACT FROM PUBLISHER]

We investigated the effect of body thickness on the electrical performance of GaSb double-gate ultrathin-body (DG-UTB) MOSFET by examining the band structure of the 12- ( $\sim 2$ nm), 24- ( $\sim 4$ nm), 36- ( $\sim 6$ nm), and 48- ( $\sim 8$ nm) atomic-layer (AL) thick GaSb. Two different surface orientations, namely, (100) and (111), were studied. sp3d5s* tight-binding model is used to calculate the band structures of GaSb MOSFET. Ballistic transport was studied using the semiclassical top-of-barrier model with applied self-consistent real-space potential across the body. First, we found that for (100) surface orientation, GaSb DG-UTB FET with body thickness of 24 ALs offered relatively larger ON-state current for various gate dielectric materials studied. However, for (111) surface orientation, 12 ALs GaSb DG-UTB FET showed the best performance due to its reasonably higher injection velocity and larger electron density. Furthermore, for the FET with a body thickness of 48 ALs and HfO2 dielectric, it was observed that the charge occupations shift toward the surface, unlike the cases of FETs with thinner body, leading to the formation of inversion charge on the surface. Finally, we compared the ON-state current of GaSb DG-UTB FET with different channel surface orientations and found that (100) surface generally outperforms (111) surface in terms of ON-state current. [ABSTRACT FROM AUTHOR]