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With the process node further scaling down, the bit cell of magnetic random access memory (MRAM) device suffers from severe failure and reliability problems due to its process variation. In this article, we explored the variability of a promising toggle spin torques MRAM (TST-MRAM) in detail, which achieves ultrafast switching speed and high endurance and is expected to be applied as upper-level caches. Our research is conducted with a 14 nm FinFET design kit, the basic performance of TST-MRAM and different pulse conditions are explored, and then the variation effect of device parameters is discussed and compared in detail as well as the write error rate (WER) under different voltages. The results demonstrate that the variation of access transistors dominates the variability, where the transistor in the spin–orbit torque (SOT) branch has a greater negative impact than the transistor in the spin transfer torque (STT) branch. To further reduce WER, a better structure with diodes of bit cell is proposed. [ABSTRACT FROM AUTHOR]

As the speed gap of the modern processor and the off-chip main memory enlarges, on-chip cache capacity increases to sustain the performance scaling. As a result, the cache power occupies a large portion of the total power budget. Spin transfer torque magnetic memory (STT-MRAM) is proposed as a promising solution for the low power cache design due to its high integration density and ultralow leakage power. Nevertheless, the high write power and latency of STT-MRAM become new barriers for the commercialization of this emerging technology. In this paper, we investigate the thermal effect on the access performance of STT-MRAM, and observe that the temperature can affect the write delay and energy significantly. Then, we explore the nonuniform cache access (NUCA) design of the chip-multiprocessors with STT-MRAM-based last level cache (LLC). A thermal aware data migration policy, called “Thermosiphon,” which takes advantage of the thermal property of STT-MRAM, is proposed to reduce the LLC write energy. This policy splits the LLC into different regions dynamically based on the thermal distribution monitored by thermal sensors available on-chip, and adaptively migrates write intensive data among different thermal regions considering the thermal gradient. Compared to the conventional NUCA design, our proposed design can save 41.2% write energy at most and 13.01% on average with negligible hardware overhead. [ABSTRACT FROM AUTHOR]

We propose a toggle spin torques magnetic random access memory (TST-MRAM) for ultrafast computing. The write operation of the TST-MRAM is achieved by applying two currents to the MTJ and a heavy metal layer, respectively, in a toggle-like manner. These two currents generate spin transfer torque (STT) and spin-orbit torque (SOT) to switch the magnetization. Thanks to the interplay effect between STT and SOT, low-energy and ultrafast write operation can be implemented without the need for the additional magnetic field. It is important to mention that both the amplitude and duration of the current flowing through the tunnel barrier can be decreased to enhance significantly the write endurance of the MTJ. The results demonstrate that the TST-MRAM is a good candidate for the upper-level caches, where the ultrafast operation and high write endurance are indispensable. [ABSTRACT FROM AUTHOR]

Ultrahigh-speed magnetization switching mechanism is strongly pursued, as it can improve the write performance of the magnetic random access memory (MRAM) and further extend the application area of spintronics. Currently, a well-studied switching mechanism is the spin transfer torque (STT), whose speed, however, is limited by an intrinsic incubation delay. Recently, spin–orbit torque (SOT) was proposed to solve the speed bottleneck of the STT. In this paper, we evaluate the potential of two types of SOT-MRAMs, whose data can be ultrafast written based on the recently discovered field-free SOT mechanisms, respectively. A cross-layer analysis is presented involving device modeling, circuit-level optimization, and architecture-level evaluation. First, the principle of the magnetization switching is analyzed with the macrospin simulation. Then, the optimization strategies at the circuit level are generalized through the SPICE-type simulation. Finally, we build up the memory architecture with the SOT-MRAMs, STT-MRAM, and static RAM. Their read/write performances are evaluated with NVSim software. It is demonstrated that one of the studied SOT-MRAMs shows the promising prospect in the non-volatile memory, especially suitable for high-capacity cache. [ABSTRACT FROM AUTHOR]

With the rapid increase of leakage currents, non-volatile memories have become competitive candidates in the next-generation computer architecture. Among them, STT-MRAM shows great promise in working memory with high density, high speed and tremendous endurance, etc. However, based on our investigations, the dynamic write power and read reliability are two critical challenges of STT-MRAM. In this work, we propose a synergistic pseudo-differential sensing (PDS) framework that employs device, circuit and architectural techniques to address these challenges. In specific, three design techniques, including cell cluster, asymmetric sensing amplifier and self-error-detection-correction, are proposed to implement the PDS framework. We show that the holistic device-circuit-architecture cross-layer co-design enables STT-MRAM to be utilized in the cache memory, benefiting from the improved density, reliability and energy-efficiency. Our experimental results show that the proposed PDS scheme improves the read margin by ∼35.6 percent, reduces the area, read latency, read energy, write latency and write power by ∼46.7, ∼9.8, ∼30.3, ∼2.3 and ∼31.1 percent respectively, compared with the typical 1T1MTJ cell structure for the cache capacity of 8 MB. In addition, the proposed PDS scheme reduces the dynamic energy by ∼32.9 percent and leakage energy by ∼830 percent, improves the IPC by ∼1.3 percent and miss rate by ∼36.9 percent respectively, compared with conventional SRAM based cache. [ABSTRACT FROM AUTHOR]

Spin-transfer torque magnetic random access memory (STT-MRAM) has emerged as a promising candidate for the next-generation high-speed, low-power, and scalable nonvolatile memory technology. Its advantageous features have attracted much attention in the area of research and development, and a number of preindustrial prototypes and small-scale products have been demonstrated. One expects to widely commercialize it in the next few years. One of the critical issues that blocks STT-MRAM’s wide commercialization is its low sensing reliability due to the relatively small tunnel magnetoresistance ratio of the magnetic tunnel junction (MTJ) and the continuously increasing process variations, especially as technology process scales down to the deep submicrometer nodes (e.g., 40 nm). In this paper, we present a variation-tolerant high-reliability sensing circuit for deep submicrometer STT-MRAM. This circuit, using triple-stage sensing and charge transfer amplification, is able to tolerate significantly the process variations and improve greatly the sensing margin by sacrificing some sensing time. Using a CMOS 40 nm design kit and a precise STT-MTJ compact model, transient and Monte Carlo simulations have been carried out to demonstrate its sensing performance. [ABSTRACT FROM AUTHOR]