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In this paper, we report measurements in Colorado and Utah of the disturbed very-low-frequency (VLF) signals from the NML Navy transmitter in North Dakota during the 2017 solar eclipse. Using an occultation mask of solar fluxes together with detailed chemistry and VLF propagation simulations, we quantify the D-region response to the eclipse, in terms of electron density variation, as well as the expected signatures of VLF transmitter signals. The VLF measurements, including an anomalous amplitude enhancement recorded in UT, can be quantitatively explained using the Wait and Spies ionospheric profile with a sharpness parameter of $\beta = 0.3$ km−1 above ~55 km and an increase in the D-region ionosphere height of $\Delta h' \simeq 8$ km. This sharpness parameter is consistent with previously reported rocket measurements and first-principles calculations. The best-fit results suggest a reduction of D-region electron density by ~90% during the eclipse in the D-region, implying an occultation of Lyman- $\alpha $ by nearly 99%. This finding agrees with detailed calculations of time-dependent obscuration factors utilizing the He 30.4-nm images from Solar Dynamics Observatory as a proxy for the distribution of Lyman- $\alpha $ across the solar disk and limb. Moreover, the present results show that subionospheric VLF propagation is sensitive to the sharpness parameter of the electron density profile in the D-region. Previously reported first-principles simulations have shown that the sharpness parameter is mostly controlled by the background concentration of minor neutral species. Thus, the VLF technique can be likely used to remotely sense these neutral species at and below the effective reflection altitudes of VLF waves. [ABSTRACT FROM AUTHOR]

The proposed fully integrated digital-intensive system on chip (SoC) allows dual-mode protocols of Bluetooth low energy (BLE) 5.0 and IEEE802.15.4 with extended-range wireless connectivity and ad hoc mesh networks for Internet-of-Things (IoT) systems in wireless sensor networks. The SoC fully integrates a dc–dc converter, LDOs, a digitally controlled crystal oscillator (DCXO), a PHY, a microcontroller (MCU), a security engine, an SRAM, and an eFlash memory. A triple-supply configuration and low-voltage circuit design enable the SoC to be applied for a wide range of battery-powered systems energy-efficiently and to extend battery lifetime. The TRX employs a low insertion-loss on-die TRX switch with impedance matching circuits, a pseudodifferential current-mode class-D PA with HD2 calibration, a low-IF RX architecture with fast AGC algorithm and complex CT- $\Delta \Sigma $ ADCs, and a low-power all-digital phase-locked loop (ADPLL) with fast settling injection LDOs and an LMS-based two-point direct frequency modulation structure. The TRX implemented in a 28-nm CMOS process achieves an output power of +10 dBm with a calibrated HD2 of −63 dBc while consuming 45 mW and sensitivities of −98 dBm in 2-Mb/s BLE and −102 dBm in 256-kb/s IEEE802.15.4 at ${10}^{-3}$ BER while consuming 6 mW. [ABSTRACT FROM AUTHOR]