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This article presents a quadrature switched/floated capacitor power amplifier (SFCPA) with deep back-off efficiency enhancement. The SFCPA is introduced to decrease the dynamic power consumption at power back-off (PBO), which could improve the system efficiency (SE). The reconfigurable self-coupling canceling transformer (RSCCT) with enhanced tuning range of turn ratio is used to achieve impedance boosting for further improved efficiency at deep PBO. Based on the proposed SFCPA, a watt-level quadrature digital power amplifier (DPA) with IQ cell sharing, hybrid Doherty, and impedance boosting is proposed for deep PBO efficiency enhancement. Implemented in 40-nm CMOS, the proposed DPA with 1.2-/2.4-V supply achieves 30.3-dBm saturated output power ($P_{\mathrm{ out}}$) with 36.6%/32.9%/29.1%/23.7%/18.6%/13.2% SE for 0-/3-/6-/9-/12-/15-dB PBOs at 2.4 GHz. For 60-MHz 256-QAM modulation signal, it delivers 23.32-dBm average output power ($P_{\mathrm{ avg}}$) with an error vector magnitude (EVM) of −31.9 dB and an average drain efficiency (DE) of 30.7%. For 40-MHz 1024-QAM signal, it shows 20.44-dBm $P_{\mathrm{ avg}}$ with an EVM of −35.9 dB and an average DE of 22.6%. [ABSTRACT FROM AUTHOR]

This article proposes a quad-core millimeter-wave (mm-wave) oscillator using E-M mixed-coupling resonance boosting. The mixed-coupling resonator is introduced to generate four reconfigurable resonances. The magnetic coupling and electric coupling are achieved by the symmetrically coupled transformer and coupling capacitor, respectively. A 2-D mode switch array is introduced to couple the quad-core and achieve the quad-mode switching without degrading the performance of the selected mode. Therefore, the reduction of phase noise and the extension of tuning range are achieved simultaneously. Meanwhile, the digitally controlled tail-resistor array is used to optimize the flicker noise up-conversion in wideband. Prototyped in 40-nm CMOS, the proposed oscillator exhibits a 73.2% tuning range from 18.6 to 40.1 GHz. The best phase noise at 1-MHz offset is −108.5 dBc/Hz, corresponding to an figure-of-merit (FoM) of 184.4 dBc/Hz and FoMT of 201.7 dBc/Hz. The variation range of FoM over the whole frequency range is 3 dB. The 1/ƒ3 phase noise corner is 220–620 kHz. [ABSTRACT FROM AUTHOR]

A quadrature digital power amplifier (PA) with hybrid Doherty and impedance boosting (HDIB) technique is presented for deep power back-off (PBO) efficiency enhancement in the complex domain. Less power-combining ways and dc power supplies are required for proposed PA comparing to previously reported works with deep PBO efficiency enhancement. A reconfigurable matching network (RMN) based on a novel reconfigurable transformer is proposed with more freedom to achieve a flexible load impedance tuning range of the sub-PAs. The characteristics of the reconfigurable transformer based on tunable inductors are analyzed. Efficiency enhancement is achieved at 3-/6-/9-/12-/15-dB PBOs without any supply switching or PA short-switches. The PA is fabricated in 40-nm CMOS technology with a core size of 0.83 mm2. Operating at 2.3–3.4 GHz, it introduces 24.2-dBm peak Pout with 38.5% peak drain efficiency (DE) at 2.8 GHz. It achieves 38.5%/29.6%/18.4% at 2.8 GHz and 34.7%/26.6%/17.8% DE at 3.3 GHz for 0-/6-/12-dB PBO, 39.3%/29.5%/14.9% at 2.8 GHz, and 35.3%/27.9%/15.9% DE at 3.3 GHz for 3-/9-/15-dB PBO, respectively. For 10-MHz 256-QAM modulation signal, it delivers 16.22-/15.50-dBm average Pout with EVM of −32.3/−33.0 dB, average DE of 24.6%/22.7%, and ACLR of −33.20/−31.54 dBc at 2.8/3.3 GHz, respectively. For 20-MHz 64 QAM modulation signal, it exhibits 16.42-/15.52-dBm average Pout with EVM of −29.1/−29.3 dB, average DE of 24.9%/22.78%, and ACLR of −30.78/−30.74 dBc at 2.8/3.3 GHz, respectively. [ABSTRACT FROM AUTHOR]

Satisfying the increasing volume of data streaming in modern wireless systems will demand energy-efficient RF front ends with gigabit data rates, high integration levels, and low cost. The power amplifier (PA) is the last door in the RF front end for both the digital and analog kingdoms, one that greatly affects the quality of service of the wireless link [1]. Thus, breaking through barriers (i.e., output power, linearity, efficiency, operation band, and even multifunction) in PA design is of paramount importance right now [2]. Consequently, with the aim of meeting the modern requirements of multistandard wireless applications, such as 5G, narrowband Internet of Things (NB-IoT), wireless local area network (WLAN), and future smart communications, various mixed-signal PAs have been developed and proposed in recent years. [ABSTRACT FROM AUTHOR]

A compact high-resolution reconfigurable phase-tuning line (RPTL) based on self-shielded 3-D interdigital capacitors is presented in this letter. Such a capacitor with high- $Q$ and self-shielded characteristics is used to implement the digitally switchable capacitor array in the RPTL, which is integrated with a coplanar waveguide and can lead to merits of the low loss, high phase-tuning resolution, and compact size. Meanwhile, the grounded shield is utilized in the RPTL to further reduce the loss. To verify the mechanisms of aforementioned structure, a 6-bit digital controlled RPTL is implemented and fabricated using a 40-nm CMOS technology. At 30 GHz, the measured loss of the proposed RPTL is 2.1 dB, while a tuning resolution of 0.38° with an RMS phase error of 0.25° is achieved. [ABSTRACT FROM AUTHOR]

A wideband hybrid mode-switching push–push oscillator with low phase noise is presented in this paper. To achieve the wide tuning range, the inductive and capacitive hybrid mode-switching technique is proposed for the first time. It introduces more freedom of design parameters (i.e., inductance and capacitance) in the resonant tank. Under certain tuning range requirement, the hybrid mode-switching oscillator achieves higher input impedance of the resonator compared to the conventional mode-switching oscillators. Meanwhile, a transformer-coupled inductor ring with symmetrical layout configuration is proposed to realize the switch-less hybrid mode switching, which further improves the circuit performance at sub-THz. Therefore, a good phase noise performance can be obtained within a wide tuning range, which leads to a relaxed tradeoff between the phase noise and tuning range. To verify the aforementioned mechanism operating at sub-THz band, a hybrid mode-switching oscillator based on the dual-mode push–push topology is proposed and fabricated in a conventional 28-nm CMOS technology. The measured results show a 21.7% tuning range with the center frequency of 169.6 GHz and a state-of-the-art FoMT of −180.6 dBc/Hz. The core circuit only occupies 0.039 mm2, while drawing 95 mW with a 0.9-V supply. [ABSTRACT FROM AUTHOR]

In this paper, two fully integrated digital power amplifiers (DPAs) intended for polar transmitters are proposed using a 40-nm CMOS technology, which achieve ultra wideband and high efficiency simultaneously. Firstly, the wideband Class-E power amplifier with nonideal characteristics is analyzed. Secondly, the design procedure of converting the nonideal Class-E model to a compact matching network is introduced for the on-chip implementation. Thirdly, the stacked-stepped-impedance transformer is utilized for the wideband output-matching network to improve the DPA power efficiency while tracking optimum load impedance. Finally, to enhance the saturated and back-off efficiency within a wideband, a novel feed-forward DPA architecture for a digital polar transmitter with multi-mode dynamic-matching (DM) network is firstly introduced and demonstrated. To verify the mechanism mentioned above, two DPAs are implemented and fabricated, which are the only reported wideband DPAs operating above 3 GHz with record fractional bandwidths, i.e., 92% and 100.8%, respectively. The proposed DPAs (i.e., DPA-I and DPA-II) exhibit peak output power of 22.2 and 22.3 dBm and peak drain efficiency of 46.2% and 47.4%, respectively, with a 1.2-V supply. In DM modes, the saturated and 6-dB back-off drain efficiency of DPA-II achieve maximum improvements of 7.5% and 5.7%, respectively. The core chip-sizes of the proposed DPAs (i.e., DPA-I and DPA-II) are 0.22 mm^2 and 0.24 mm^2, respectively. [ABSTRACT FROM PUBLISHER]