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SnS2 and SnS are two-dimensional (2D) semiconductors with distinct properties, as they exhibit a different type of conduction. They are of interest for applications in nanoelectronics, optoelectronics and sensors. To enable these applications, the deposition of SnS2 and SnS layers with a well-controlled phase, crystallinity and thickness at the nanometer level is required on large-area substrates. Chemical vapor deposition (CVD) of SnS2 and SnS using SnCl4 and H2S has previously been reported to give micrometer level polycrystalline SnS2 and SnS layers, which were insulating due to the uncontrolled grain orientations. In this work, we investigate the formation mechanism and phase control of nanometer level 2D SnS2 and SnS by SnCl4/H2S CVD. Nanometer level and phase-pure 2D hexagonal SnS2 and orthorhombic SnS layers are obtained. The SnSx phase depends on both the temperature and the H2S/SnCl4 concentration ratio. Compared to the formation of the SnS2 phase, the formation of the SnS phase is favorable at higher temperature and, surprisingly, at a higher H2S/SnCl4 concentration ratio. This is explained by the catalytic decomposition of H2S by SnS2 with the formation of H2, where the as such generated H2 reduces SnS2 to SnS at temperatures equal to or higher than 350 °C. By adjusting the conditions of the CVD process, the product can be tuned to either n-type SnS2 or p-type SnS, as demonstrated by back-gated field effect transistors. [ABSTRACT FROM AUTHOR]

Large area MoS2 films with tunable physical-chemical properties are grown on dielectric substrates by annealing of ultrathin Mo layers in the presence of a sulfur-containing gaseous precursor. Different growth conditions are found to have a significant impact on material properties, including chemical composition, roughness, and grain sizes, thus shedding light on critical parameters that govern sulfurization processes for the synthesis of large area 2D transition metal dichalcogenides. Optimized growth conditions in combination with the use of single crystal sapphire substrates with atomically flat interface result in the formation of oriented MoS2 films with improved quality and electrical performance. On the basis of this versatile synthesis technique, an original double-step process is presented for the synthesis of WS2/MoS2 vertical heterostructures. Good uniformity of layers over large area has enabled first isolation of defects by electron spin resonance spectroscopy with densities correlated with mobility degradation and the first experimental characterization of the band alignment at the interfaces of MoS2, WS2, and their vertical stacks with the underlying SiO2 insulator. [ABSTRACT FROM AUTHOR]

2D transition metal dichalcogenide based van der Waals materials are promising candidates to realize tunnel field effect transistors (TFETs) with a steep subthreshold swing (SS) for low‐power applications. Their atomically flat, self‐passivated layers offer potentially defect free interlayer tunneling. There are still several issues that need to be addressed to experimentally achieve a steep SS, e.g., the Schottky contacts, impact of thick layers, and device architecture with respect to gate configuration. This paper resolves these challenges by experimentally demonstrating MoS2/MoTe2 TFETs and their electrical characteristics, in conjunction with ab initio simulations and surface Kelvin probe microscopy. The Schottky barrier's effect at the contact regions are isolated by fabricating individual buried gates below the contacts. Devices with different top and bottom gate configurations are produced to understand the impact of gate placement on the heterostructure characteristics. Quantum transport simulations are performed on MoS2/MoTe2 multilayer stack to evaluate the impact of multiple layers on TFET performance, effect of gate placement, and the mechanism behind indirect tunneling over the heterojunction region. This work highlights the influence of the Schottky contacts, multiple layers and the role of different gate configurations on the band‐to‐band tunneling phenomenon in 2D heterojunction TFETs. [ABSTRACT FROM AUTHOR]