Search

Artificial Intelligence harnessed from knowledge graphs and logical reasoning yields excellent interpretability as well as proficient reasoning and decision-making capabilities. Declarative rules, such as Prolog and Datalog, are prevalent formalisms for expressing expert knowledge and are employed in numerous systems due to their inherent explicability. This thesis introduces Evoda, a novel, evolutionary-based algorithm conceived for rule mining on large-scale knowledge graphs (KGs) and classification problems. While current methodologies examine the rule hypothesis space undertake exhaustive searches, subjected to heuristic and syntactic limitations on the rule language, thereby constraining the quality of the derived rules. In this research, the rule hypothesis space is broadened from conventional path rules to encompass general Datalog rules, with Evoda as a new metaheuristic genetic logic programming algorithm. Rule evaluation is extended from the restrictive closed world assumption (CWA) to a more practical open world assumption (OWA). Experimental results, assessed using various evaluation metrics on multiple real-world knowledge graphs, underscore Evoda's proficiency in mining superior quality rules, its enhanced precision in predictions within the enlarged rule space, and its significant strides in efficiency and scalability, handling up to 22 million facts within mere seconds. Additionally, we proposed and demonstrated that existential rules accelerate the learning rate through the inclusion of intermediate states. It surpasses several state-of-the-art rule mining and embedding models in KG completion tasks. From a machine learning standpoint, Evoda necessitates only a select few hyperparameters that display discernible patterns, thus obviating the need for hyperparameter tuning. Moreover, Evoda demonstrates exceptional performance on diverse classification datasets from academic to industry applications. In summary, this work accentuates the feasibility, effectiveness, and efficiency of the newly proposed evolutionary learning framework.

This paper presents a generative architecture for general-purpose room layouts that can be treated as geometric definitions of dungeons, mansions, shooter levels and more. The motivation behind this work is to provide a design tool for virtual environments that combines aspects of controllability, expressivity and generality. Towards that end, a two-tier level representation is realized, with a graph-based design specification constraining and guiding the generated geometries, facilitated by constrained evolutionary search. Expressivity is secured through quality-diversity search which can provide the designer with a broad variety of level layouts to choose from. Finally, the generator is general-purpose as it can produce layouts based on different types of static grid structures or as freeform, curved structures through an adaptive Voronoi diagram that is evolved along with the level itself. The method is tested on a variety of design specifications and grid types, and results show that even with complex design constraints or malleable grids the algorithm can produce a broad variety of levels., peer-reviewed

Evolutionary algorithms (EAs) have been with us for several decades and are highly popular given that they have proved competitive in the face of challenging problems’ features such as deceptiveness, multiple local optima, among other characteristics. However, it is necessary to define multiple hyper-parameter values to have a working EA, which is a drawback for many practitioners. In the case of genetic programming (GP), an EA for the evolution of models and programs, hyper-parameter optimization has been extensively studied only recently. This work builds on recent findings and explores the hyper-parameter space of a specific GP system called neat-GP that controls model size. This is conducted using two large sets of symbolic regression benchmark problems to evaluate system performance, while hyper-parameter optimization is carried out using three variants of the iterated F-Race algorithm, for the first time applied to GP. From all the automatic parametrizations produced by optimization process, several findings are drawn. Automatic parametrizations do not outperform the manual configuration in many cases, and overall, the differences are not substantial in terms of testing error. Moreover, finding parametrizations that produce highly accurate models that are also compact is not trivially done, at least if the hyper-parameter optimization process (F-Race) is only guided by predictive error. This work is intended to foster more research and scrutiny of hyper-parameters in EAs, in general, and GP, in particular.

Multi-objective evolutionary algorithms are widely used by researchers and practitioners to solve multi-objective optimization problems (MOPs), since they require minimal assumptions and are capable of computing a finite size approximation of the entire solution set in one run of the algorithm. So far, however, the adequate treatment of equality constraints has played a minor role. Equality constraints are particular since they typically reduce the dimension of the search space, which causes problems for stochastic search algorithms such as evolutionary strategies. In this paper, we show that multi-objective evolutionary algorithms hybridized with continuation-like techniques lead to fast and reliable numerical solvers. For this, we first propose three new problems with different characteristics that are indeed hard to solve by evolutionary algorithms. Next, we develop a variant of NSGA-II with a continuation method. We present numerical results on several equality-constrained MOPs to show that the resulting method is highly competitive to state-of-the-art evolutionary algorithms.

Scaling petaflop supercomputers to exascale requires a 500x increase in FLOPS, but at the cost of only a 3x increase in the total power consumption. In addition, computing systems implemented with nanometer scale multi-gate field effect transistors are increasingly integrating heterogeneous cores, GPUs, and accelerators. The power delivery and energy management of such complex chip multi-processors (CMP) is, therefore, a challenging research task spanning across the system, architecture, circuits, and device stack. A set of on-chip energy management techniques that are similar to supply side and demand side management in a SMART grid is developed. The techniques span the circuit and system layers. Intelligence is introduced in the operation of the on-chip power distribution network (PDN) to sense variations in the computational activity across cores and reconfigure the PDN to optimize the energy efficiency. A circuit level technique that improves the energy efficiency through the implementation of under-provisioned on-chip voltage regulators (OCVRs) interconnected through a switch network is developed. An operating system level task scheduling heuristic distributes the workloads on the cores such that the required reconfiguration of the PDN is minimized. SPICE simulations indicate up to a 44% reduction in the energy consumption of the CMP. An evolving on-chip power delivery methodology where reference voltages of the OCVRs are controlled through a particle swarm optimizer (PSO) is developed. The PSO negates the effects of transistor aging and process, temperature, and power supply noise induced variation in the load circuit, OCVRs, and on-chip timing sensors. The simulation results indicate an average reduction of 35% and 5% in, respectively, the power consumption and operating temperature of the voltage domains. In addition, the end of life of the voltage domain is prolonged due to a mean reduction in the aging induced Vth shift of 40%. Novel circuit techniques to detect and set the power supply voltages and suppress power supply noise are developed. The run-time circuit techniques for power supply voltage detection and clamping are demonstrated for a heterogeneous 3-D integrated circuit through SPICE simulation of a device plane in a 22 nm technology and a power plane in a 45 nm technology. The power supply voltages of less than 1 V are successfully set and provided as a reference to an OCVR within 500 ns of initiating an active state and with variation of less than 1% in the reference voltage. Noise on the power supply is suppressed through the use of hyperabrupt p-n junction varactors as on-chip decoupling capacitors. The voltage droops and overshoots on the on chip power distribution network are suppressed by up to 60% as compared to metal insulator metal (MIM) or deep trench decoupling capacitors of the same capacitance. With approximately 42% and 15% of the data center power consumed by, respectively, the processors and the cooling system, the run-time energy management techniques developed in this thesis have significant potential to reduce the running cost of exascale data centers.