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This paper presents a rectifier-less ac–dc energy harvesting circuit capable of harvesting energy from multiple low-voltage piezoelectric transducers (PETs). Synchronous electric charge extraction technique, with bidirectional switches, is adopted to achieve rectifier-less ac–dc direct conversion. The inductor is engaged only during the voltage peak of the PET output for a short period of time and therefore, a single inductor can be shared by multiple transducers. A split-capacitor charging topology is employed to harvest both positive and negative half-cycle energies, without the use of an input rectifier. In addition, a self-startup function is incorporated to kick-start the system from low input voltages. A prototype has been implemented with off-the-shelf components. Energy harvesting from three PET energy sources with different resonance frequencies is demonstrated. A peak overall power conversion efficiency of 79% is achieved with a system self-startup voltage of 650 mV. [ABSTRACT FROM AUTHOR]

A novel detection framework named Markov Clustering Network (MCN) is proposed for fast and robust scene text detection. Different from the traditional top-down scene text detection approaches that inherit from the classic object detection, MCN detects scene text objects in a bottom-up manner. MCN predicts instance-level bounding boxes by firstly converting an image into a stochastic flow graph where Markov Clustering is performed based on the predicted stochastic flows. The stochastic flows encode the local correlation and semantic information of scene text objects. An object is modeled as strongly connected nodes by flows, which allows flexible and bottom-up detection for scale-varying and rotated text objects without prior knowledge of object size. The flow prediction is supported by the advanced Convolutional Neural Networks architectures and Position-aware spatial attention mechanism, which provides enhanced flow prediction by adaptively fusing spatial representations. The experimental evaluation on public benchmarks shows that our MCN method achieves the state-of-art performance on public benchmarks, especially in retrieving long and oriented texts. [ABSTRACT FROM AUTHOR]

ABSTRACT The advances in semiconductor fabrication technologies have enabled the integration of Lamb-wave resonator on silicon substrate. But such integration has led to additional parasitic effects to the Lamb-wave resonators. The availability of an efficient equivalent-circuit model is thus vital. This paper proposes a modified hybrid π-type/Butterworth-Van Dyke (PiBVD) model. Compared with the conventional PiBVD model, the modified PiBVD model accounts for the parasitic inductances of the bonding wires. It therefore provides better accuracy when characterizing Lamb-wave resonators over a wide frequency range. Experiment results have also verified that the modified PiBVD model has better fitting on Y11 (input reflection factor in Y-parameter matrix). This improvement is greatly beneficial for resonator analysis and circuit designs © 2017 Wiley Periodicals, Inc. Microwave Opt Technol Lett 59:703-706, 2017 [ABSTRACT FROM AUTHOR]

The scene text interpretation is a critical part of the natural scene interpretation. Currently, most of the existing work is based on high-end graphics processing units (GPUs) implementation, which is commonly used on the server side. However, in Internet of Things (IoT) application scenarios, the communication overhead from the edge device to the server is quite large, which sometimes even dominates the total processing time. Hence, the edge-computing oriented design is needed to solve this problem. In this paper, we present an architectural design and implementation of a natural scene text interpretation (NSTI) accelerator, which can classify and localize the text region on pixel-level efficiently in real-time on mobile devices. To target the real-time and low-latency processing, the binary convolutional encoder–decoder network is adopted as the core architecture to enable massive parallelism due to its binary feature. Massively parallelized computations and a highly pipelined data flow control enhance its latency and throughput performance. In addition, all the binarized intermediate results and parameters are stored on chip to eliminate the power consumption and latency overhead of the off-chip communication. The NSTI accelerator is implemented in a 40 nm CMOS technology, which can process scene text images (size of 128 × 32) at 34 fps and latency of 40 ms for pixelwise interpretation with the pixelwise classification accuracy over 90% on ICDAR-03 and ICDAR-13 dataset. The real energy-efficiency is 698 GOP/s/W and the peak energy-efficiency can get up to 7825 GOP/s/W. The proposed accelerator is 7 times more energy efficient than its optimized GPU-based implementation counterpart, while maintaining a real-time throughput with latency of 40 ms. [ABSTRACT FROM AUTHOR]

A large capacitive load amplifier with enhanced active-feedback frequency compensation is proposed in this paper. The enhancement is achieved through using a wide-bandwidth scalar circuit to increase the transconductance of the output stage so that the overall bandwidth of the amplifier can be extended considerably. Implemented in a standard CMOS 130-nm technology, with a supply of 0.7 V and consuming 27 μA of current, the amplifier drives a load capacitor of 15 nF. No on-chip resistor is needed; only a 0.91-pF compensation capacitor is used to maintain stability. The achieved gain-bandwidth product and phase margin are 1.28 MHz and 66.9°, respectively. Moreover, the slew rate is 0.263 V/μs. The active chip area is 0.0056 mm2. Copyright © 2017 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

A dominant-pole substitution (DPS) technique for low-dropout regulator (LDO) is proposed in this paper. The DPS technique involves signal-current feedforward and amplification such that an ultralow-frequency zero is generated to cancel the dominant pole of LDO, while a higher frequency pole substitutes in and becomes the new dominant pole. With DPS, the loop bandwidth of the proposed LDO can be significantly extended, while a standard value and large output capacitor for transient purpose can still be used. The resultant LDO benefits from both the fast response time due to the wide loop bandwidth and the large charge reservoir from the output capacitor to achieve the significant enhancement in the dynamic performances. Implemented with a commercial 0.18-μm CMOS technology, the proposed LDO with DPS is validated to be capable of delivering 100 mA at 1.0-V output from a 1.2-V supply, with current efficiency of 99.86%. Experimental results also show that the error voltage at the output undergoing 100 mA of load transient in 10-ns edge time is about 25 mV. Line transient responses reveal that no more than 20-mV instantaneous changes at the output when the supply voltage swings between 1.2 and 1.8 V in 100 ns. The power-supply rejection ratio at 3 MHz is −47 dB. [ABSTRACT FROM AUTHOR]