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This paper presents a novel structure and design of a full custom digital chip that generates the three-phase sinusoidal pulse width modulation (SPWM) waveform with variable voltage and variable frequency (VVVF) control. The voltage and frequency are simultaneously controlled with constant v/f ratio. The frequency range is from 5Hz up to 75Hz and the voltage also changes proportionally. In this way, three modes including fix, manual setting and closed loop control have been defined that provide simple implementation and high flexibility for the IC. The synchronous modulation is used (p=63) in which there are 63 pulses for every complete sinusoidal cycle. Considering the dead time between the complementary signals that reach the switches on an inverter’s leg, the result of the simulation shows the elimination of low order harmonics with value of 40 dB for each of the SPWM outputs. The method used for generating sinusoidal waveform and variable frequency generator circuit and also the approach taken for controlling amplitude and frequency simultaneously are completely novel. The chip has been designed using 0.35µm CMOS standard technology with approximately 15000 transistors on chip. The complete circuit consumes 680µm × 570µm of chip area and 48mW of power dissipation.

This study presents a spread spectrum clock generator (SSCG) circuit for high‐speed applications. The proposed SSCG adopts a phased locked loop with two dual voltage‐controlled oscillators and a frequency modulation loop implemented with a novel control unit to achieve the desired spectrum‐spreading profile. The control unit consists of an analogue charge pump‐based frequency comparator that can determine the deviation of spread spectrum clock frequency from the reference frequency. Using this analogue frequency comparator simplifies the SSCG control unit and mitigates the design constraints, particularly the speed requirements of SSCG control unit. Hence, the structure becomes a suitable solution for high‐speed applications. The proposed SSCG is tailored for USB3.1 standard with −4000 to −5000 ppm down spreading at 5 GHz clock frequency and 30–33 kHz modulation frequencies. The circuit is designed in TSMC 0.18 μm 1P6M CMOS process that occupies 0.13 mm2 active area. Based on simulation results, with a 1.8 V supply, it consumes 53.46 mW. The RMS value of absolute jitter at 5 GHz output of non‐spread spectrum is 1.1 ps rms, and the EMI reduction is 22.7 dB with −5000 ppm down spread. The simulation results of the proposed system are compared with recent works. [ABSTRACT FROM AUTHOR]

Analog implementation of fuzzy logic controllers (FLCs) is the most efficient method when speed, power, and area are critical. Inference engine (IE) usually takes a large part of total die area when the FLC has a large number of rules. In this paper, a method is proposed to reduce size of the IE in analog implementations of FLCs. Since only a small number of rules may be fired simultaneously, thus a few inference blocks (IBs) may work at the same time in an IE. In the proposed method, reduction in size of the IE is achieved by sharing a few IBs between a large number of rules. To test the proposed method, a standard FLC is designed using both the regular method and the proposed method. By using the proposed method, total power consumption and active area are reduced by factors of 2.31 and 2.15, respectively. Moreover, inference speed is improved by a factor of 3.8 and output error is reduced by a factor of 2.5. All simulations have been performed in HSPICE using level 49 models for 0.35 um CMOS process with a 3.3V power supply. [ABSTRACT FROM AUTHOR]

In this paper, a low jitter 16-phases delay locked loop (DLL) is proposed based on a simple and sensitive phase detector (PD). Dead-zone of the proposed PD is improved in compare to the conventional structures where the pulse generator postpones PD response and reduces the sensitivity. Also, the conventional structure of charge pumps is modified to inject small charge throughout the continuous outputs of PD. Smaller bias current is provided in charge pump via subtracting tail currents of intentionally mismatched di®erential pairs. Duty cycle of output di®erential phases is adjusted to around 50% using common mode setting strategy on delay elements. Simulation results confirm that DLL loop can provide 16-phases in frequency range of 80 to 410 MHz, consuming total power of 3.5 and 5.6mW, respectively. The dead-zone of PD is also reduced from 80 to 14 ps when the pulse generator section is eliminated. Also, RMS jitter of about 45 and 1.76 ps are obtained at 80 and 410 MHz, respectively, when the supply voltage is subject to around 40mV peak-to-peak noise disturbances. The proposed DLL can be implemented in less than 0.05mm² active area in a 0.18μm CMOS technology. [ABSTRACT FROM AUTHOR]