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This article introduces a holistic and systematic design methodology tailored to the 10 kV silicon carbide (SiC) mosfet power modules. Multiobjective optimization was achieved with enhanced electric-field (E-field) distribution, minimized common-mode (CM) parasitic capacitance, and reduced system-level parasitic inductances. The proposed approach encompasses two innovative techniques: 1) an electric-potential-oriented module-system interface to reduce system-level parasitic inductance while maximizing insulation capability; 2) stacked substrates with patterned middle layer copper to alleviate the E-field concentration at the triple-point and reduce the maximum E-field without compromising on thermal resistance. The effectiveness of these innovative approaches is substantiated through the development of a 10 kV SiC mosfet power module. The optimized layout presents well-balanced 5.6 nH power loop inductance with embedded decoupling capacitors and record-low 28 pF CM parasitic capacitance, attributed to the middle layer pattern structure. In addition, a 38.6% E-field concentration reduction at the triple-point is identified compared to conventional stacked substrates. Experimental validation showcases its robust voltage insulation capability with a leakage current of 0.87 μA at 10 kV, a 33 kV dc, and 25 kV ac surface flashover for worst-case system fault conditions. The partial discharge inception voltage of the proposed middle layer patterned stacked substrates is verified at 16.8 kVrms. Dynamic performance validation through a double-pulse test at 5 kV showcases negligible ringing and voltage overshoot. All these exceptional attributes position the packaged 10 kV SiC mosfet power module as an exemplary choice for MV power electronics applications.

We developed a hybrid single- and two-phase capillary-based microcooler consisting of parallel microchannels with hydrophilic wicks for power electronics. The presented approach overcomes the conventional pumped-only flow two-phase cooling limitations, such as flow instabilities and large temperature superheat in confined microchannels. We further conducted a parametric study of the microcooler and investigated the boiling dynamics of capillary flow using high-speed imaging. While the proof-of-concept microcooler is demonstrated on a copper substrate and free-form liquid supply setup, it can be easily implemented in the copper layer of a direct bonded copper (DBC) substrate of the power module package. The capillary-driven microchannel cooler demonstrates a significant performance improvement compared to conventional single/two-phase closed-microchannel coolers, achieving maximum heat flux ~700 W/cm2, superheat ~30 °C, and the target two-phase thermal resistance ~0.043 cm $^{2}\cdot ^{\circ }\text{C}$ /W. The capillary-based microcooler achieves vapor quality > 0.9, utilizing $50\times $ smaller flowrates compared to two/single-phase conventional microchannel coolers. Successful implementation of the capillary-driven microcooler would result in significant downsizing of the cooling system for electric vehicles.

A strategy for providing semi-direct cooling of SiC MOSFETs in an extremely power dense half-bridge module, while also serving as a source terminal interconnection is presented. This bussing structure with integrated cooling function provides topside (source) connection to 16 paralleled devices within a low inductance, 1.7 kV rated power module. Dielectric fluid coolant (HFE7500) in the microchannel (MC) manifold sustains the voltage discharge risk in the fluid but while not introduce risks associated with flooding the module with coolant. Meanwhile, it also achieves a low thermal resistance pathway between the device and to coolant as a single-phase coolant. Thermal characterization has been performed illustrating an effective thermal resistance of 0.54 cm2-°C/W across the 16 devices, with ample room for increased performance with optimized device topside attachment. This cooling approach inside of a bussing connector has the opportunity to increase module + cooler power density up to $4\times $ – $5\times $ of a traditional single-sided module, as well as reduce the thermal coupling effects inside a module.

Silicon carbide (SiC) power devices have been extensively for high-power-density application scenarios. To increase the current rating, SiC devices are usually connected in parallel. However, the mismatching current brought by unbalanced electrical parameters can increase the current stress of a device and pose a reliability concern for the converter system. Aiming at addressing the current imbalance for paralleled SiC devices, this article reports the application of an improved active gate driver (AGD) on the paralleled SiC MOSFETs to address the current imbalance problems. The three-level driver voltage can minimize the overshoot voltage and current. The adjustable turn-on voltage and gate signal delay time can realize the current sharing of both static and dynamic processes. Current sensors and a digital controller are utilized for close-loop control. The functionality of the proposed AGD is validated in continuous operating experiments.

Cryogenic power electronics is regarded as the next step to improve the converter efficiency and power density. It is advantageous in many different applications, including aerospace, renewable energy, transportation and so on. Among all different semiconductors, gallium nitride (GaN) was found more advantageous with significant loss reduction at cryogenic temperature. In this paper, overcurrent test is performed and analyzed for a high-efficient commercial GaN high electron mobility transistor (HEMT). The experimental results demonstrate a significant improvement of the device overcurrent capability at cryogenic temperature (from 160 A at room temperature to 250 A at cryogenic temperature). The operating mechanisms behind the overcurrent test are investigated and discussed. Finally, a 5 kW GaN HEMT based cryogenic Buck converter is built and tested. Maximum efficiency of 98.5% is achieved at 1.5 kW output power and around 1% efficiency improvement can be achieved when compared to room temperature operation. Another GaN HEMT based four-switch Buck-boost converter is evaluated at cryogenic temperature, maximum efficiency improvement of 1.5% is observed when compared to room temperature.

We report for the first time on an aluminum nitride/gallium nitride (AlN/GaN) heterostructure as a microscale Hall effect sensor for current sensing applications in extreme environments. The AlN/GaN devices demonstrated high signal linearity as a function of the magnetic field across a temperature range from -193 °C to 407 °C. The measured room temperature (RT) supply voltage-related sensitivity ( ${S}_{\text {svrs}}{)}$ and supply current-related sensitivity ( ${S}_{\text {scrs}}{)}$ are 0.055 T-1 and 32 AV-1T-1, respectively. The supply power-related sensitivity ( ${S}_{\text {sprs}}{)}$ is 1.4 VW-1T-1 above 40-mW input bias, which is higher than that of the Al0.2Ga0.8N/GaN device. The designed AlN/GaN micro-Hall sensor is further determined to have a lower power consumption and higher temperature sensitivity than equivalent Al0.2Ga0.8N/GaN Hall devices. When operated in an ac bias mode, the rise time of the Hall sensor was found to be 102 ns, corresponding to a frequency bandwidth of 9.8 MHz. We also observed a phase shift between an applied magnetic field and the Hall sensor signal, which can potentially be helpful to monitor ac line currents.

Recent studies in power electronic design automation have introduced various models for parasitic extraction of multichip power module layouts. However, none of these studies considers the eddy current effect in the direct-bonded-copper substrate, accounting for 40%–50% errors in the extraction result. This work introduces a methodology for eddy-current consideration through numerical simulation and regression modeling. The regression model utilized in the characterization process in this work is fast and memory-efficient compared to the finite element approach. This characterization process can improve the accuracy of any partial element model without sacrificing performance. Combining this characterization process and partial element approach achieves less than 10% extraction error compared to Ansys Q3D while showing a maximum speedup of $35\times $ and $17\times $ more memory efficiency. This method also significantly reduces the number of elements in the extracted netlist and the complexity of loop evaluation. This method is attractive for use with optimization routines and, therefore, has been used successfully in a layout optimization tool.