1. Analysis and Verilog-A Modeling of Floating-Gate Transistors
- Author
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Sayma Nowshin Chowdhury, Matthew Chen, and Sahil Shah
- Subjects
Floating-gate transistors ,Verilog-A ,analog synapses ,Electric apparatus and materials. Electric circuits. Electric networks ,TK452-454.4 - Abstract
Floating-gate transistors provide non-volatile analog storage in standard CMOS processes and are crucial in the development of reconfigurable Systems on Chips (SoCs), programmable analog structures, analog neural networks, and mixed-signal neuromorphic circuits. Designing and fabricating these circuits typically involves extensive SPICE-based simulations, yet integrating and calibrating floating-gate transistors post-fabrication is a common practice. To bridge this gap, we present a Verilog-A model based on empirical measurements for a floating-gate transistor fabricated using a 65 nm CMOS process. This model incorporates mechanisms for hot-electron injection and Fowler-Nordheim tunneling, and accurately predicts retention time, thus facilitating the design of adaptive peripheral circuits. Our findings offer insights into optimizing floating-gate transistors for enhanced programming efficiency and reduced area consumption.
- Published
- 2025
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