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Summary An analog background calibration approach is presented for the full calibration of pipeline analog‐to‐digital converters (ADCs). A well‐trained neural network acts close to the ideal 1.5‐bit stage, and its residue is compared with the real 1.5‐bit stage including gain error and amplifier nonlinearities. The detected error is used to compensate for the imperfect residue using four calibration polynomial coefficients. The corrected residue enters the second stage of the pipeline ADC and follows a normal path to achieve high resolution. The introduced structure is verified in a 12‐bit pipelined ADC composed of 11 stages; the first 10 stages have a 1.5‐bit structure, while the last stage is a 2‐bit flash. The sampling frequency is 100 MHz, and 10% non‐ideal factors (5% for each of the nonlinear and gain errors and 10% for the aggregated error) are considered for the first stage, while the input is 19.5 MHz sinusoidal waveform. A random noise is applied to the input to limit the effective number of bits (ENOB) to almost 11.8. The evaluation parameters of the ADC are extracted, signal‐to‐noise and distortion ratio increases from 39.14 to 72.91 dB, spurious free dynamic range improves from 40.94 to 79.69 dB, and the ENOB enhances from 6.2 to 11.82. The presented mechanism shows an acceptable accuracy in the high‐speed and high‐resolution ADCs. [ABSTRACT FROM AUTHOR]

An inexact 6-transistor full adder (FA) cell is presented. It is low-power and gives full-swing outputs because of the applied gate diffusion input (GDI) along with the dynamic threshold (DT) techniques. The FA which has three errors is used in a 10-transistor inexact 4:2 compressor based on the stacking circuit idea. The implementation by a 16-nm carbon nanotube field-effect transistor (CNTFET) technology shows a small area of 0.027 and $0.045~\mu \text{m}^{\mathrm{ 2}}$ for the FA and compressor, respectively. A new approximate sum of absolute differences (SADs) block is presented by the FA and compressor. The average power, power-delay-product (PDP), and peak signal-to-noise ratio (PSNR) of the SAD are 6.80 mW, 33.86 nJ, and 42.98 dB, respectively, which confirm its efficiency for bioimages difference detection. [ABSTRACT FROM AUTHOR]

Approximate computing (AC) is an emerging technique in arithmetic circuits. In this letter, a new AC-based full adder (FA) circuit is presented with 12 transistors, 150mm]Please confirm or add details for any funding or financial support for the research of this article. -160mm]If you haven’t done so already, please make sure you have submitted a video graphical abstract (GA) for your paper, along with a caption and overlay image. The GA will be displayed on your articles abstract page on IEEE Xplore. Note that captions cannot exceed 1800 characters (including spaces). Overlay images are usually a screenshot of your video that best represents the video. This is for readers who may not have access to video-viewing software. 0.239 $\mu \text{m}^{2}$ of area, and two errors in the outputs. In the proposed FA, the gate diffusion input (GDI) and dynamic-threshold (DT) techniques are applied using the carbon nanotube field-effect transistor (CNTFET) technology. Accuracy metrics, such as normalized mean error distance (NMED) and mean relative error distance (MRED) along with circuitry parameters of power-delay-product (PDP), energy-delay-product (EDP), and power-delay-area-product (PDAP), confirm the efficiency of the proposed FA for complex structures. The proposed FA is embedded in a ripple carry adder (RCA) by various numbers of approximate bits (NABs), and then the accuracy and circuitry parameters are extracted. Compared to the state-of-the-art designs, the high-efficient behavior of the proposed FA is proved when it is used in image processing applications. [ABSTRACT FROM AUTHOR]

Magnetic resonance imaging (MRI) is a high‐quality medical image that is used to detect brain tumours in a complex and time‐consuming manner. In this study, a back propagation neural network (BPNN) along with the Levenberg–Marquardt algorithm (LMA) is proposed to classify MRIs and diagnose brain tumours in a simple and fast process. The BPNN has 10 neurons in the hidden layer, and the default function of the feedforward feeds is mean squared error (MSE). The LMA is optimized as a multivariable adaptive approach and considerably decreases the MSE of the BPNN, so the errors of the tumour classification are diminished. The proposed method follows four steps including preprocessing, skull removal, feature extraction, and classification. The input MRIs are converted to greyscale, resized, and thresholding is performed in the preprocessing step and followed by skull removal. Morphological operations of closing, opening, and dilation are used to segment abnormal areas in the MRIs, and the opening operator recognizes the tumour more accurately. Using statistical analysis and a grey‐level co‐occurrence matrix (GLCM) 12 features are extracted from the MRIs and used as the inputs of the BPNN. To evaluate the proposed method, 670 normal and 670 abnormal brain MRIs are used as input data, and the classification is performed in 0.494 s. The accuracy, sensitivity, specificity, precision, dice, recall, and MSE are 98.7%, 97.61%, 99.7%, 97.61%, 98.6%, 97.61%, and 0.005, respectively. The approach is accurate and fast for medical images classification. [ABSTRACT FROM AUTHOR]

A new low‐power and high‐speed multiplier is presented based on the voltage over scaling (VOS) technique and new 5:3 and 7:3 counter cells. The VOS reduces power consumption in digital circuits, but different voltage levels of the VOS increase the delay in different stages of a multiplier. Hence, the proposed counters are implemented by the gate‐diffusion input technique to solve the speed limitation of the VOS‐based circuits. The proposed GDI‐based 5:3 and 7:3 counters save power and reduce the area by 2x and 2.5x, respectively. To prevent the threshold voltage (Vth) drop in the suggested GDI‐based circuits, carbon nanotube field‐effect transistor (CNTFET) technology is used. In the counters, the chirality vector and tubes of the CNTFETs are properly adjusted to attain full‐swing outputs with high driving capability. Also, their validation against heat distribution under different time intervals, as a major issue in the CNTFET technology is investigated, and their very low sensitivity is confirmed. The low complexity, high stability and efficient performance of the presented counter cells introduce the proposed VOS‐CNTFET‐GDI‐based multiplier as an alternative to the previous designs. [ABSTRACT FROM AUTHOR]