98 results on '"Vector clock"'
Search Results
2. The Bloom Clock to Characterize Causality in Distributed Systems
- Author
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Kshemkalyani, Ajay D., Misra, Anshuman, Kacprzyk, Janusz, Series Editor, Pal, Nikhil R., Advisory Editor, Bello Perez, Rafael, Advisory Editor, Corchado, Emilio S., Advisory Editor, Hagras, Hani, Advisory Editor, Kóczy, László T., Advisory Editor, Kreinovich, Vladik, Advisory Editor, Lin, Chin-Teng, Advisory Editor, Lu, Jie, Advisory Editor, Melin, Patricia, Advisory Editor, Nedjah, Nadia, Advisory Editor, Nguyen, Ngoc Thanh, Advisory Editor, Wang, Jun, Advisory Editor, Barolli, Leonard, editor, Li, Kin Fun, editor, Enokido, Tomoya, editor, and Takizawa, Makoto, editor
- Published
- 2021
- Full Text
- View/download PDF
3. The Bloom Clock for Causality Testing
- Author
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Misra, Anshuman, Kshemkalyani, Ajay D., Goos, Gerhard, Founding Editor, Hartmanis, Juris, Founding Editor, Bertino, Elisa, Editorial Board Member, Gao, Wen, Editorial Board Member, Steffen, Bernhard, Editorial Board Member, Woeginger, Gerhard, Editorial Board Member, Yung, Moti, Editorial Board Member, Goswami, Diganta, editor, and Hoang, Truong Anh, editor
- Published
- 2021
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- View/download PDF
4. On the Growth of the Prime Numbers Based Encoded Vector Clock
- Author
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Kshemkalyani, Ajay D., Voleti, Bhargav, Hutchison, David, Series Editor, Kanade, Takeo, Series Editor, Kittler, Josef, Series Editor, Kleinberg, Jon M., Series Editor, Mattern, Friedemann, Series Editor, Mitchell, John C., Series Editor, Naor, Moni, Series Editor, Pandu Rangan, C., Series Editor, Steffen, Bernhard, Series Editor, Terzopoulos, Demetri, Series Editor, Tygar, Doug, Series Editor, Weikum, Gerhard, Series Editor, Fahrnberger, Günter, editor, Gopinathan, Sapna, editor, and Parida, Laxmi, editor
- Published
- 2019
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- View/download PDF
5. Probabilistic Causal Message Ordering
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Mostéfaoui, Achour, Weiss, Stéphane, Hutchison, David, Series editor, Kanade, Takeo, Series editor, Kittler, Josef, Series editor, Kleinberg, Jon M., Series editor, Mattern, Friedemann, Series editor, Mitchell, John C., Series editor, Naor, Moni, Series editor, Pandu Rangan, C., Series editor, Steffen, Bernhard, Series editor, Terzopoulos, Demetri, Series editor, Tygar, Doug, Series editor, Weikum, Gerhard, Series editor, and Malyshkin, Victor, editor
- Published
- 2017
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- View/download PDF
6. Using Insights on Cloud Service Quality
- Author
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Bermbach, David, Wittern, Erik, Tai, Stefan, Bermbach, David, Wittern, Erik, and Tai, Stefan
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- 2017
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7. Prime clock: Encoded vector clock to characterize causality in distributed systems.
- Author
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Kshemkalyani, Ajay D., Shen, Min, and Voleti, Bhargav
- Subjects
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LARGE scale systems , *CLOCKS & watches , *PRIME numbers , *AUTOREGRESSIVE models - Abstract
The vector clock is a fundamental tool for tracking causality in distributed applications. Unfortunately, it does not scale well to large systems because each process needs to maintain a vector of size n , where n is the total number of processes in the system. To address this problem, we propose the prime clock, which is based on the encoding of the vector clock using prime numbers and uses a single number to represent vector time. We propose the operations on the encoded vector clock (EVC). We then show how to timestamp global states and how to perform operations on the global states using the EVC. Using a theoretical analysis and a simulation model, we evaluate the growth rate of the size of the EVC. The EVC is seen to grow very fast and hence it does not appear to offer a general purpose practical replacement of vector clocks. To address this drawback, we propose several scalability techniques for the EVC that can allow the use of the EVC in practical applications. We then present two case studies of detecting memory consistency errors in MPI one-sided applications and of dynamic race detection in multi-threaded environments, that use a combination of two of these scalability techniques. The results show that the EVC is not just a theoretical concept, but it is applicable to practical problems and can compete in terms of both space and time requirements with other known protocols. • We propose a single integer encoded vector clock (EVC) based on prime numbers. • We give various operations on EVC and evaluate the complexity of EVC. • EVCs tend to grow very fast. • We give scalability techniques for reducing the size of EVC. • Two case studies justify that EVC can perform better than vector clock. [ABSTRACT FROM AUTHOR]
- Published
- 2020
- Full Text
- View/download PDF
8. Consistency Models
- Author
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Harrison, Guy and Harrison, Guy
- Published
- 2015
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9. Data Models and Storage
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Harrison, Guy and Harrison, Guy
- Published
- 2015
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10. Resettable Encoded Vector Clock for Causality Analysis With an Application to Dynamic Race Detection
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Tommaso Pozzetti and Ajay D. Kshemkalyani
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Theoretical computer science ,Computational Theory and Mathematics ,Shared memory ,Hardware and Architecture ,Computer science ,Vector clock ,Signal Processing ,Scalar (mathematics) ,Message passing ,Prime number ,Logical clock - Abstract
Causality tracking among events is a fundamental challenge in distributed environments. Much previous work on this subject has focused on designing an efficient and scalable protocol to represent logical time. Several implementations of logical clocks have been proposed, most recently the Encoded Vector Clock (EVC), a protocol to encode Vector Clocks (VC) in scalar numbers through the use of prime numbers, to improve performance and scalability. We propose and formalize the concept of Resettable Encoded Vector Clock (REVC), a new logical clock implementation, which builds on the EVC to tackle its very high growth rate issue. We show how our REVC can be applied in both shared memory systems and message passing systems to achieve a consistent logical clock. We show, through practical examples, the advantage of REVC’s growth rate with respect to EVC’s growth rate. Finally, we show a practical application of the REVC to the dynamic race detection problem in multi-threaded environments. We compare our tool to the currently existing VC-based tool $\text{DJIT}^+$ DJIT + to show how the REVC can help in achieving higher performance with respect to the Vector Clock.
- Published
- 2021
11. Prime clock: Encoded vector clock to characterize causality in distributed systems
- Author
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Bhargav Voleti, Min Shen, and Ajay D. Kshemkalyani
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Computer Networks and Communications ,Vector clock ,Computer science ,Distributed computing ,Process (computing) ,020206 networking & telecommunications ,02 engineering and technology ,Prime (order theory) ,Theoretical Computer Science ,Causality (physics) ,Consistency (database systems) ,Artificial Intelligence ,Hardware and Architecture ,0202 electrical engineering, electronic engineering, information engineering ,020201 artificial intelligence & image processing ,Software - Abstract
The vector clock is a fundamental tool for tracking causality in distributed applications. Unfortunately, it does not scale well to large systems because each process needs to maintain a vector of size n , where n is the total number of processes in the system. To address this problem, we propose the prime clock, which is based on the encoding of the vector clock using prime numbers and uses a single number to represent vector time. We propose the operations on the encoded vector clock (EVC). We then show how to timestamp global states and how to perform operations on the global states using the EVC. Using a theoretical analysis and a simulation model, we evaluate the growth rate of the size of the EVC. The EVC is seen to grow very fast and hence it does not appear to offer a general purpose practical replacement of vector clocks. To address this drawback, we propose several scalability techniques for the EVC that can allow the use of the EVC in practical applications. We then present two case studies of detecting memory consistency errors in MPI one-sided applications and of dynamic race detection in multi-threaded environments, that use a combination of two of these scalability techniques. The results show that the EVC is not just a theoretical concept, but it is applicable to practical problems and can compete in terms of both space and time requirements with other known protocols.
- Published
- 2020
12. Lamport Timestamp Digital Signature based Mutual Node Authentication for Secured Data Communication IN WSN
- Author
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Antony Cynthia
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General Computer Science ,Digital signature ,Computer science ,business.industry ,Vector clock ,General Engineering ,Node authentication ,business ,Computer network - Published
- 2020
13. Scalability approaches for causal multicast: a survey.
- Author
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Juan-Marín, Rubén, Decker, Hendrik, Armendáriz-Íñigo, José, Bernabéu-Aubán, José, and Muñoz-Escoí, Francesc
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SCALABILITY , *INTERNET searching , *ELECTRONIC commerce , *INTERNET in public administration , *MULTICASTING (Computer networks) - Abstract
Many distributed services need to be scalable: internet search, electronic commerce, e-government $$\ldots $$ In order to achieve scalability those applications rely on replicated components. Because of the dynamics of growth and volatility of customer markets, applications need to be hosted by adaptive systems. In particular, the scalability of the reliable multicast mechanisms used for supporting the consistency of replicas is of crucial importance. Reliable multicast may propagate updates in a pre-defined order (e.g., FIFO, total or causal). Since total order needs more communication rounds than causal order, the latter appears to be the preferable candidate for achieving multicast scalability, although the consistency guarantees based on causal order are weaker than those of total order. This paper provides a historical survey of different scalability approaches for reliable causal multicast protocols. [ABSTRACT FROM AUTHOR]
- Published
- 2016
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14. Preserving stabilization while practically bounding state space using incorruptible partially synchronized clocks
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Vidhya Tekken Valapil and Sandeep S. Kulkarni
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Computer Networks and Communications ,Computer science ,Vector clock ,Clock drift ,0102 computer and information sciences ,Topology ,01 natural sciences ,Theoretical Computer Science ,03 medical and health sciences ,Variable (computer science) ,0302 clinical medicine ,Computational Theory and Mathematics ,010201 computation theory & mathematics ,Hardware and Architecture ,030220 oncology & carcinogenesis ,Bounded function ,Logical clock ,State space ,Transient (computer programming) ,Mutual exclusion - Abstract
Stabilization is a key dependability property for dealing with unanticipated transient faults, as it guarantees that even in the presence of such faults, the system will recover to states where it satisfies its specification. One of the desirable attributes of stabilization is the use of bounded space for each variable. In this paper, we present an algorithm that transforms a stabilizing program that uses variables with unbounded domain into a stabilizing program that uses bounded variables by using partially synchronized physical time. Specifically, our algorithm relies on bounded clock drift $$\epsilon $$ among processes and message delivery that either delivers the message in time $$\delta $$ or loses it. If we let $$\epsilon $$ to be as much as 100 s and $$\delta $$ to be as much as 1 h, this property is satisfied by any practical system. While non-stabilizing programs (that do not handle transient faults) can deal with unbounded variables by assigning large enough but bounded space, stabilizing programs—that need to deal with arbitrary transient faults—cannot do the same since a transient fault may corrupt the variable to its maximum value. We show that our transformation algorithm is applicable to several problems including logical clocks, vector clocks, mutual exclusion, diffusing computations, and so on. Moreover, our approach can also be used to bound counters used in an earlier work by Katz and Perry for adding stabilization to a non-stabilizing program. By combining our algorithm with that work by Katz and Perry and by assuming incorruptible partially synchronized clocks, it would be possible to provide stabilization for a rich class of problems, by assigning large enough but bounded space for variables.
- Published
- 2019
15. A time-stamping system to detect memory consistency errors in MPI one-sided applications
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Karl Fürlinger, Thanh-Dang Diep, Kien Trung Pham, and Nam Thoai
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MPICH ,Computer Networks and Communications ,Vector clock ,Computer science ,010103 numerical & computational mathematics ,computer.software_genre ,Supercomputer ,01 natural sciences ,Computer Graphics and Computer-Aided Design ,Execution time ,Theoretical Computer Science ,010101 applied mathematics ,Consistency (database systems) ,Computer engineering ,Artificial Intelligence ,Hardware and Architecture ,Synchronization (computer science) ,Scalability ,0101 mathematics ,computer ,Time complexity ,Software ,Debugger - Abstract
Many high performance computing applications have been developed by using MPI one-sided communication. The separation between data movement and synchronization poses enormous challenges for programmers in preserving the reliability of programs. One of those challenges is the detection of memory consistency errors, which are a notorious bug, degrading the reliability and performance of programs. Even an MPI expert can easily make these mistakes. The lockopts bug, which occurred in an RMA test case of the MPICH MPI implementation, is an example for this situation. MC-Checker is the most effective debugger in solving the memory consistency errors. MC-Checker did ignore the transitive ordering of the happened-before relation to ensure the acceptable overheads in terms of time complexity. Consequently, MC-Checker is prone to error due to the source of false positives attributable to the ignorance of the transitive ordering of the happened-before relation. To address this issue, we propose a time-stamping system based on the encoded vector clock to help preserve the full happened-before relation with reasonable overhead. The system is implemented in MC-CChecker, which is an enhancement of MC-Checker. The experimental findings prove that MC-CChecker not only effectively detects memory consistency errors like MC-Checker did, but also completely eliminates the potential source of false positives, which is a major limitation of MC-Checker while still retaining acceptable overheads of execution time and memory usage. Especially, MC-CChecker is fairly scalable when processing a large number of trace files generated from running the lockopts up to 8192 processes.
- Published
- 2019
16. Virtual time and its application to data race detection.
- Author
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YU Zhen, SU Xiaohong, WANG Tiantian, and MA Peijun
- Abstract
Aiming at applying virtual time mechanism to data race detection, a model is proposed to uniformly describe different implementation forms of virtual time. We firstly establish an abstract model for a distributed execution. Based on this model, we give a unified description on virtual time's three basic implementation forms; scalar time system, vector time system and matrix time system. Furthermore, we take vector time system and matrix time system for examples to illustrate four optimization techniques for virtual time. At last, we discuss the problems to be solved when applying virtual time to data races detection in shared - memory concurrent systems and four application examples. The model proposed in this paper unifies different implementation forms of virtual time and reduces the difficulty of applying virtual time to data race detection. [ABSTRACT FROM AUTHOR]
- Published
- 2015
- Full Text
- View/download PDF
17. The Bloom Clock for Causality Testing
- Author
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Ajay D. Kshemkalyani and Anshuman Misra
- Subjects
020203 distributed computing ,Computer science ,Vector clock ,Probabilistic logic ,020206 networking & telecommunications ,02 engineering and technology ,Bloom filter ,Causality (physics) ,0202 electrical engineering, electronic engineering, information engineering ,False positive paradox ,Overhead (computing) ,False positive rate ,Timestamp ,Algorithm - Abstract
Testing for causality between events in distributed executions is a fundamental problem. Vector clocks solve this problem but do not scale well. The probabilistic Bloom clock can determine causality between events with lower space, time, and message-space overhead than vector clock; however, predictions suffer from false positives. We give the protocol for the Bloom clock based on Counting Bloom filters and study its properties including the probabilities of a positive outcome and a false positive. We show the results of extensive experiments to determine how these above probabilities vary as a function of the Bloom timestamps of the two events being tested, and to determine the accuracy, precision, and false positive rate of a slice of the execution containing events in the temporal proximity of each other. Based on these experiments, we make recommendations for the setting of the Bloom clock parameters. We postulate the causality spread hypothesis from the application’s perspective to indicate whether Bloom clocks will be suitable for correct predictions with high confidence. The Bloom clock design can serve as a viable space-, time-, and message-space-efficient alternative to vector clocks if false positives can be tolerated by an application.
- Published
- 2020
18. CoNICE: Consensus in Intermittently-Connected Environments by Exploiting Naming with Application to Emergency Response
- Author
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Kadangode K. Ramakrishnan and Mohammad Jahanian
- Subjects
Consensus algorithm ,Emergency response ,Vector clock ,Paxos ,Computer science ,Distributed computing ,Schema (psychology) ,Scalability ,0202 electrical engineering, electronic engineering, information engineering ,020206 networking & telecommunications ,020201 artificial intelligence & image processing ,02 engineering and technology - Abstract
In many scenarios, information must be disseminated over intermittently-connected environments when network infrastructure becomes unavailable. Example scenarios include disasters in which first responders need to send updates about their critical tasks. If such updates pertain to a shared data set (e.g., pins on a map), their consistent dissemination is important. We can achieve this through causal ordering and consensus. Popular consensus algorithms, such as Paxos and Raft, are most suited for connected environments with reliable links. While some work has been done on designing consensus algorithms for intermittently-connected environments, such as the One-Third Rule (OTR) algorithm, there is need to improve their efficiency and timely completion. We propose CoNICE, a framework to ensure consistent dissemination of updates among users in intermittently-connected, infrastructure-less environments. It achieves efficiency by exploiting hierarchical namespaces for faster convergence, and lower communication overhead. CoNICE provides three levels of consistency to users' views, namely replication, causality and agreement. It uses epidemic propagation to provide adequate replication ratios, and optimizes and extends Vector Clocks to provide causality. To ensure agreement, CoNICE extends basic OTR to support long-term fragmentation and critical decision invalidation scenarios. We integrate the multilevel consistency schema of CoNICE, with a naming schema that follows a topic hierarchy-based dissemination framework, to improve functionality and performance. Performing city-scale simulation experiments, we demonstrate that CoNICE is effective in achieving its consistency goals, and is efficient and scalable in the time for convergence and utilized network resources.
- Published
- 2020
19. Rapid Consensus Structure: Continuous Common Knowledge in Asynchronous Distributed Systems
- Author
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Kiyoung Jang, Jiho Park, Sang-Min Choi, and Chihyun Park
- Subjects
Software_OPERATINGSYSTEMS ,Lamport timestamps ,Computer science ,General Mathematics ,02 engineering and technology ,01 natural sciences ,consensus algorithm ,symbols.namesake ,gossip protocol ,0202 electrical engineering, electronic engineering, information engineering ,Computer Science (miscellaneous) ,Gossip protocol ,0101 mathematics ,Engineering (miscellaneous) ,Byzantine fault tolerance ,Protocol (object-oriented programming) ,continuous common knowledge ,Vector clock ,business.industry ,Node (networking) ,lcsh:Mathematics ,010102 general mathematics ,Directed acyclic graph ,lcsh:QA1-939 ,lamport timestamp ,Asynchronous communication ,byzantine fault tolerance ,symbols ,directed acyclic graph ,020201 artificial intelligence & image processing ,business ,Computer network - Abstract
A distributed system guarantees the acceptance of Byzantine fault tolerance (BFT) for information transmission. Practical BFT (pBFT) and asynchronous BFT (aBFT) are among the various available forms of BFT. Distributed systems generally share information with all participating nodes. After information is shared, the systems reshare it. Thus, ensuring BFT consumes a considerable amount of time. Herein, we propose Decision search protocols that apply the gossip protocol, denoted by DecisionBFT, for distributed networks with guaranteed BFT. Each protocol in DecisionBFT is completely asynchronous and leaderless, it has an eventual consensus but no round-robin or proof-of-work. The core concept of the proposed technology is the consensus structure, which is based on the directed acyclic graph (DAG) and gossip protocol. In the most general form, each node in the algorithm has a set of k neighbors of most preference. When receiving transactions, a node creates and connects an event block with all its neighbors. Each event block is signed by the hashes of the creating node and its k peers. The consensus structure of the event blocks utilizes a DAG, which guarantees aBFT. The proposed framework uses Lamport timestamps and concurrent common knowledge. Further, an example of a Decision search algorithm, based on the gossip protocol DecisionBFT, is presented. The proposed DecisionBFT protocol can reach a consensus when 2/3 of all participants agree to an event block without any additional communication overhead. The DecisionBFT protocol relies on a cost function to identify the k peers and generate the DAG-based consensus structure. By creating a dynamic flag table that stores connection information between blocks, the gossip protocol achieves a consensus in fewer steps than that in the case of the existing aBFT protocol.
- Published
- 2020
20. The Bloom Clock to Characterize Causality in Distributed Systems
- Author
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Ajay D. Kshemkalyani and Anshuman Misra
- Subjects
020203 distributed computing ,Computer science ,Vector clock ,Probabilistic logic ,020206 networking & telecommunications ,Data_CODINGANDINFORMATIONTHEORY ,02 engineering and technology ,Bloom filter ,Causality (physics) ,0202 electrical engineering, electronic engineering, information engineering ,False positive paradox ,Overhead (computing) ,False positive rate ,Bloom ,Algorithm - Abstract
Determining the causality between events in distributed executions is a fundamental problem. Vector clocks solve this problem but do not scale well. The probabilistic Bloom filter data structure can be used as a Bloom clock to determine causality between events with lower space overhead than vector clock; however, the Bloom filter and hence the Bloom clock naturally suffer from false positives. We give a formal protocol of the Bloom clock based on Counting Bloom filters and study its properties. We formulate the probabilities of a positive outcome, a positive being false, and a false positive for Bloom clocks as a function of the corresponding vector clocks, as well as their estimates as a function of the Bloom clocks. We also indicate how to estimate the accuracy, precision, and false positive rate of an execution slice that is identified by the Bloom timestamps of two events.
- Published
- 2020
21. Distributed computation of vector clocks in Petri net unfoldings for test selection
- Author
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Agnes Madalinski, Stefan Schwoon, Loïg Jezequel, Laboratoire des Sciences du Numérique de Nantes (LS2N), IMT Atlantique Bretagne-Pays de la Loire (IMT Atlantique), Institut Mines-Télécom [Paris] (IMT)-Institut Mines-Télécom [Paris] (IMT)-Université de Nantes - UFR des Sciences et des Techniques (UN UFR ST), Université de Nantes (UN)-Université de Nantes (UN)-École Centrale de Nantes (ECN)-Centre National de la Recherche Scientifique (CNRS), Otto-von-Guericke University [Magdeburg] (OVGU), Laboratoire Spécification et Vérification (LSV), and Université Paris-Saclay-Centre National de la Recherche Scientifique (CNRS)-Ecole Normale Supérieure Paris-Saclay (ENS Paris Saclay)
- Subjects
030213 general clinical medicine ,0209 industrial biotechnology ,Computer science ,Vector clock ,Computation ,Distributed computing ,02 engineering and technology ,Petri net ,03 medical and health sciences ,Task (computing) ,020901 industrial engineering & automation ,0302 clinical medicine ,Control and Systems Engineering ,TheoryofComputation_LOGICSANDMEANINGSOFPROGRAMS ,Modeling and Simulation ,Test selection ,[INFO]Computer Science [cs] ,Electrical and Electronic Engineering ,ComputingMilieux_MISCELLANEOUS - Abstract
It has been shown that annotating Petri nets unfoldings with time stamps allows to build distributed testers for distributed systems. However, the construction of the annotated unfolding of a distributed system currently remains a centralized task. In this paper we extend a distributed unfolding technique in order to annotate the resulting unfolding with time stamps. This allows distributed construction of distributed testers for distributed systems.
- Published
- 2020
22. Atomicity Checking in Linear Time using Vector Clocks
- Author
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Mahesh Viswanathan and Umang Mathur
- Subjects
FOS: Computer and information sciences ,Atomicity ,Computer Science - Programming Languages ,Speedup ,Computer science ,Vector clock ,Concurrency ,020207 software engineering ,02 engineering and technology ,Parallel computing ,Software Engineering (cs.SE) ,Computer Science - Software Engineering ,Serializability ,020204 information systems ,0202 electrical engineering, electronic engineering, information engineering ,Dynamic program analysis ,Graph (abstract data type) ,Time complexity ,Computer Science::Databases ,Programming Languages (cs.PL) - Abstract
Multi-threaded programs are challenging to write. Developers often need to reason about a prohibitively large number of thread interleavings to reason about the behavior of software. A non-interference property like atomicity can reduce this interleaving space by ensuring that any execution is equivalent to an execution where all atomic blocks are executed serially. We consider the well studied notion of conflict serializability for dynamically checking atomicity. Existing algorithms detect violations of conflict serializability by detecting cycles in a graph of transactions observed in a given execution. The number of edges in such a graph can grow quadratically with the length of the trace making the analysis not scalable. In this paper, we present AeroDrome, a novel single pass linear time algorithm that uses vector clocks to detect violations of conflict serializability in an online setting. Experiments show that AeroDrome scales to traces with a large number of events with significant speedup.
- Published
- 2020
23. What happens-after the first race? enhancing the predictive power of happens-before based dynamic race detection
- Author
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Mahesh Viswanathan, Dileep Kini, and Umang Mathur
- Subjects
Soundness ,Theoretical computer science ,Relation (database) ,Computer science ,Vector clock ,Concurrency ,020207 software engineering ,02 engineering and technology ,020204 information systems ,0202 electrical engineering, electronic engineering, information engineering ,False positive paradox ,Dynamic program analysis ,Overhead (computing) ,Safety, Risk, Reliability and Quality ,Time complexity ,Software - Abstract
Dynamic race detection is the problem of determining if an observed program execution reveals the presence of a data race in a program. The classical approach to solving this problem is to detect if there is a pair of conflicting memory accesses that are unordered by Lamport’s happens-before (HB) relation. HB based race detection is known to not report false positives, i.e., it is sound. However, the soundness guarantee of HB only promises that the first pair of unordered, conflicting events is a schedulable data race. That is, there can be pairs of HB-unordered conflicting data accesses that are not schedulable races because there is no reordering of the events of the execution, where the events in race can be executed immediately after each other. We introduce a new partial order, called schedulable happens-before (SHB) that exactly characterizes the pairs of schedulable data races — every pair of conflicting data accesses that are identified by SHB can be scheduled, and every HB-race that can be scheduled is identified by SHB. Thus, the SHB partial order is truly sound. We present a linear time, vector clock algorithm to detect schedulable races using SHB. Our experiments demonstrate the value of our algorithm for dynamic race detection — SHB incurs only little performance overhead and can scale to executions from real-world software applications without compromising soundness.
- Published
- 2018
24. Analysis of Bounds on Hybrid Vector Clocks
- Author
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Duong N. Nguyen, Sandeep S. Kulkarni, Sorrachai Yingchareonthawornchai, and Murat Demirbas
- Subjects
020203 distributed computing ,Computer science ,Vector clock ,Order (ring theory) ,Window (computing) ,02 engineering and technology ,Delay differential equation ,Topology ,Synchronization ,Causality (physics) ,Computational Theory and Mathematics ,Hardware and Architecture ,020204 information systems ,Signal Processing ,0202 electrical engineering, electronic engineering, information engineering ,Logical clock - Abstract
Hybrid vector clock(s) (HVC) provide a mechanism to combine the theory and practice of distributed systems. Improving on traditional vector clock(s) (VC), HVC utilizes synchronized physical clocks to reduce the size by focusing only on causality where the physical time associated with two events is within a given uncertainty window $\epsilon$ and letting physical clock alone determine the order of events that are outside the uncertainty window. In this paper, we develop a model for determining the bounds on the size of HVC. Our model uses four parameters, $\epsilon$ : uncertainty window, $\delta$ : message delay, $\alpha$ : communication frequency and $n$ : number of nodes in the system. We derive the size of HVC in terms of a delay differential equation, and show that the size predicted by our model is almost identical to the results obtained by simulation. We also identify closed form solutions that provide tight lower and upper bounds for useful special cases. We show that for many practical applications and deployment environments in Amazon EC2, the size of HVC remains only as a couple entries and substantially less than $n$ . Finally, although the analytical results rely on a specific communication pattern they are useful in evaluating size of HVC in different communication scenarios.
- Published
- 2018
25. Clock synchronization in wireless sensor networks using least common multiple
- Author
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Nikhath Tabassum, Geetha D. Devanagavi, and Rajashekhar C. Biradar
- Subjects
Frame synchronization (video) ,Computer science ,Vector clock ,Real-time computing ,Clock drift ,020206 networking & telecommunications ,02 engineering and technology ,Digital clock manager ,Clock skew ,Clock synchronization ,Clock domain crossing ,0202 electrical engineering, electronic engineering, information engineering ,020201 artificial intelligence & image processing ,Self-clocking signal ,Electrical and Electronic Engineering - Abstract
In this research, we propose the Clock Synchronization by Least Common Multiple (CSLCM) method to remove the clock offset and clock skew among the sensor nodes. The proposed CSLCM enables the nodes to reach a network synchronization time by calculating the least common multiple of their Clock Time Period (CTP). The network is organized into clusters and every node reaches the network synchronization time using its own CTP. Simulation results show that, the CSLCM algorithm is more efficient compared to the Average Time Synchronization with Pairwise messages (ATSP) in terms of accuracy, communication overhead, and computation overhead.
- Published
- 2017
26. Maximum Likelihood Estimation of Clock Skew in Wireless Sensor Networks With Periodical Clock Correction Under Exponential Delays
- Author
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Baoguo Wang, Haiyong Zeng, Heng Wang, Min Li, and Ping Wang
- Subjects
Vector clock ,Synchronization networks ,Computer science ,020208 electrical & electronic engineering ,Clock drift ,Skew ,Matrix clock ,020206 networking & telecommunications ,02 engineering and technology ,Digital clock manager ,Clock skew ,Timing failure ,Clock synchronization ,Synchronization ,Control theory ,Signal Processing ,0202 electrical engineering, electronic engineering, information engineering ,Self-clocking signal ,Electrical and Electronic Engineering ,Algorithm - Abstract
Time synchronization is crucial for wireless sensor networks (WSNs) since it maintains data consistency, coordination, and enables other fundamental operations. Over the last decade, a number of powerful time synchronization algorithms have been proposed for clock accuracy optimization by using signal processing techniques. However, most of these algorithms attempt to estimate the clock phase offset and skew and do not correct the node's local clock at every timing packet exchange before the clock parameters are jointly estimated, which reduces the network synchronization accuracy during the estimation of clock parameters and limits the applicability of the synchronization algorithms for some practical sensor networks where a global time scale is consistently required. Motivated by this, this paper investigates the synchronization scheme of having inactive nodes overhearing the pairwise sender-receiver time synchronization based on acknowledgement with clock correction at every synchronization. Assuming exponential random delays, the maximum likelihood estimators (MLEs) of clock skew and the corresponding approximate Cramer-Rao lower bounds (CRLBs) for active and overhearing nodes are derived. In addition, we also consider a linear synchronization model that the clock skew is directly estimated. Simulation results verify the efficiency of the clock skew estimators.
- Published
- 2017
27. A Novel Method of Clock Synchronization in Distributed Systems
- Author
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Niu Meng-jie, Chen Xin, Ren Yanqiu (仁艳秋), Li Gun, and Chai Yang-shun
- Subjects
Physics ,0209 industrial biotechnology ,Vector clock ,Distributed computing ,Clock drift ,Matrix clock ,Astronomy and Astrophysics ,02 engineering and technology ,Digital clock manager ,Clock synchronization ,Computer Science::Hardware Architecture ,020901 industrial engineering & automation ,Space and Planetary Science ,Clock domain crossing ,0202 electrical engineering, electronic engineering, information engineering ,020201 artificial intelligence & image processing ,Master clock ,Self-clocking signal - Abstract
Time synchronization plays an important role in the spacecraft formation flight and constellation autonomous navigation, etc. For the application of clock synchronization in a network system, it is not always true that all the observed nodes in the network are interconnected, therefore, it is difficult to achieve the high-precision time synchronization of a network system in the condition that a certain node can only obtain the measurement information of clock from a single neighboring node, but cannot obtain it from other nodes. Aiming at this problem, a novel method of high-precision time synchronization in a network system is proposed. In this paper, each clock is regarded as a node in the network system, and based on the definition of different topological structures of a distributed system, the three control algorithms of time synchronization under the following three cases are designed: without a master clock (reference clock), with a master clock (reference clock), and with a fixed communication delay in the network system. And the validity of the designed clock synchronization protocol is proved by both stability analysis and numerical simulation.
- Published
- 2017
28. Timestamp Free Synchronization With Sub-Tick Accuracy in the Presence of Discrete Clocks
- Author
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Werner Haselmayr, Branislav Rudic, Andreas Springer, Nino Palaoro, and Bernhard Etzlinger
- Subjects
Computer science ,Vector clock ,Applied Mathematics ,020208 electrical & electronic engineering ,Real-time computing ,Clock drift ,Matrix clock ,020206 networking & telecommunications ,02 engineering and technology ,Propagation delay ,Digital clock manager ,Clock skew ,Synchronization ,Clock synchronization ,Computer Science Applications ,Computer Science::Hardware Architecture ,Clock domain crossing ,0202 electrical engineering, electronic engineering, information engineering ,Self-clocking signal ,Electrical and Electronic Engineering - Abstract
Timestamp free clock synchronization in a master–slave network, i.e., synchronization where no timestamps are exchanged between the nodes, is considered. For highly accurate synchronization, a novel discrete-valued clock model is introduced. It is based on the observation that clocks are discrete counters in digital wireless radios. Considering this model, it is shown that the round-trip time (RTT) measurements follow specific pulse or step shaped functions. The estimated parameters of these RTT functions are used to determine the clock parameters (clock skew and phase) and the propagation delay. Numerical analysis illustrate that when RTT measurements are collected using discrete-valued clocks, the proposed estimation schemes outperform estimators derived from the continuous clock model, which is used in the state-of-the-art methods. Moreover, the presented scheme performs similar to recently presented discrete-valued clock approaches with more stringent hardware assumption. The correctness of the proposed models is validated through hardware experiments.
- Published
- 2017
29. Cluster Head selection Based Routing Protocol for VANET Using Bully Algorithm and Lamport Timestamp
- Author
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Pramodh Kavisha Dharmawardena and Zhanjie Wang
- Subjects
Routing protocol ,Vehicular ad hoc network ,business.industry ,Head (linguistics) ,Computer science ,Vector clock ,020302 automobile design & engineering ,020206 networking & telecommunications ,02 engineering and technology ,0203 mechanical engineering ,0202 electrical engineering, electronic engineering, information engineering ,Cluster (physics) ,Bully algorithm ,business ,Selection (genetic algorithm) ,Computer network - Published
- 2017
30. Boundary optimization of buffered clock trees for low power
- Author
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Joohan Kim and Taewhan Kim
- Subjects
Synchronous circuit ,Computer science ,Vector clock ,Clock drift ,0211 other engineering and technologies ,Clock gating ,02 engineering and technology ,Digital clock manager ,Topology ,Clock skew ,020202 computer hardware & architecture ,Hardware and Architecture ,Clock domain crossing ,0202 electrical engineering, electronic engineering, information engineering ,Electronic engineering ,Electrical and Electronic Engineering ,Software ,Hardware_LOGICDESIGN ,021106 design practice & management ,CPU multiplier - Abstract
The work solves a new problem of optimizing the boundary of buffered clock trees, which has not been addressed in the design automation as yet. Precisely, we want to show that the clock cells that directly drive flip-flops should not necessarily be buffers. By taking into account the internal structure of flip-flops, we can have a freedom of choosing either buffers or inverters for the cell implementation from library. This in fact leads to cancel out the two inverters, one in the driving buffer and another in each flip-flop, thereby reducing the power consumption on the clock tree, including flip-flops. We generalize this idea to look into the possibility of co-optimizing the driving buffers and flip-flops together to reduce the clock power at the boundary of clock trees, and propose an effective four-step synthesis algorithm of clock tree boundary for low power. By applying our proposed technique to benchmark circuits, it is observed that the clock power is able to be reduced by 4.45 % ~ 6.33 % further on average without timing violation.
- Published
- 2017
31. An efficient validation approach for quasi-synchronous checkpointing oriented to distributed diagnosability
- Author
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Saul E. Pomares Hernandez, Hatem Hadj Kacem, Ahmed Hadj Kacem, Houda Khlif, Alberto Calixto Simon, Cédric Eichler, Unité de Recherche en développement et contrôle d'applications distribuées (REDCAD), École Nationale d'Ingénieurs de Sfax | National School of Engineers of Sfax (ENIS), Équipe Services et Architectures pour Réseaux Avancés (LAAS-SARA), Laboratoire d'analyse et d'architecture des systèmes (LAAS), Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Institut National des Sciences Appliquées - Toulouse (INSA Toulouse), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées, Universidad del papaloapan (UNPA), Universidad del papaloapan, Université Toulouse Capitole (UT Capitole), Université de Toulouse (UT)-Université de Toulouse (UT)-Institut National des Sciences Appliquées - Toulouse (INSA Toulouse), Institut National des Sciences Appliquées (INSA)-Université de Toulouse (UT)-Institut National des Sciences Appliquées (INSA)-Université Toulouse - Jean Jaurès (UT2J), Université de Toulouse (UT)-Université Toulouse III - Paul Sabatier (UT3), Université de Toulouse (UT)-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université de Toulouse (UT)-Université Toulouse Capitole (UT Capitole), and Université de Toulouse (UT)
- Subjects
Graph rewriting ,Correctness ,Theoretical computer science ,Vector clock ,Computer science ,Distributed computing ,Local variable ,020207 software engineering ,02 engineering and technology ,Graph ,Autonomic computing ,[INFO.INFO-NI]Computer Science [cs]/Networking and Internet Architecture [cs.NI] ,Dependency graph ,Validation rule ,Hardware and Architecture ,0202 electrical engineering, electronic engineering, information engineering ,020201 artificial intelligence & image processing ,[INFO.INFO-DC]Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC] ,Software ,Information Systems - Abstract
Quasi-synchronous checkpointing algorithms are classified into: SZPF, ZPF and ZCF.We propose a validation approach to detect the previously mentioned properties.We model an algorithm execution into the HBR graph and IDR graph.We designed two sets of validation rules to work over the HBR graph and IDR graph.A lower cost is achieved using the IDR graph which is the minimal causal graph. The autonomic computing paradigm is oriented towards enabling complex distributed systems to manage themselves, even in faulty situations. The diagnosability analysis is a priori a study through which a system can be self-aware about its current state. It is from the determination of a consistent state that a system can take some action to repair or reconfigure itself. Nevertheless, in a distributed system it is hard to determine consistent states since we cannot observe simultaneously all the local variables of different processes. In this context, the challenge is to efficiently monitor the system execution over time to capture trace information in order to determine if the system accomplishes both functional and non-functional requirements. Quasi-synchronous checkpointing is a technique that collects information from which a system can establish consistent snapshots. Based on this technique, several checkpointing algorithms have been developed. According to the checkpoint properties detected and ensured, they are classified into: Strictly Z-Path Free (SZPF), Z-Path Free (ZPF) and Z-Cycle Free (ZCF). Generally, the method adopted for the performance evaluation of checkpointing algorithms involves simulation. However, few works have been designed to validate their correctness. In this paper, we propose an efficient validation approach based on a graph transformation oriented towards the automatic detection of the previously mentioned properties. To achieve this, we took the vector clocks resulting from an algorithm execution, and we modeled them into the happened-before graph and the immediate dependency graph (which is the minimal causal graph). Then, we designed a set of transformation rules to verify if in these graphs, the algorithm is exempt from non-desirable patterns, such as Z-paths or Z-cycles, according to the case.
- Published
- 2016
32. Predicting all data race pairs for a specific schedule
- Author
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Martin Sulzmann and Kai Stadtmüller
- Subjects
Sequence ,Schedule ,Relation (database) ,Vector clock ,Computer science ,Concurrency ,State (computer science) ,Algorithm ,Time complexity ,TRACE (psycholinguistics) - Abstract
We consider the problem of data race prediction where the program's behavior is represented by a trace. A trace is a sequence of program events recorded during the execution of the program. We employ the schedulable happens-before relation to characterize all pairs of events that are in a race for the schedule as manifested in the trace. Compared to the classic happens-before relation, the schedulable happens-before relations properly takes care of write-read dependencies and thus avoids false positives. The challenge is to efficiently identify all (schedulable) data race pairs. We present a refined linear time vector clock algorithm to predict many of the schedulable data race pairs. We introduce a quadratic time post-processing algorithm to predict all remaining data race pairs. This improves the state of the art in the area and our experiments show that our approach scales to real-world examples. Thus, the user can systematically examine and fix all program locations that are in a race for a particular schedule.
- Published
- 2019
33. AggrePlay: efficient record and replay of multi-threaded programs
- Author
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Ernest Pobee and W. K. Chan
- Subjects
High memory ,Vector clock ,Computer science ,020204 information systems ,Multithreading ,Concurrency ,Suite ,0202 electrical engineering, electronic engineering, information engineering ,020207 software engineering ,02 engineering and technology ,Parallel computing ,Thread (computing) ,Multi threaded - Abstract
Deterministic replay presents challenges and often results in high memory and runtime overheads. Previous studies deterministically reproduce program outputs often only after several replay iterations or may produce a non-deterministic sequence of output to external sources. In this paper, we propose AggrePlay, a deterministic replay technique which is based on recording read-write interleavings leveraging thread-local determinism and summarized read values. During the record phase, AggrePlay records a read count vector clock for each thread on each memory location. Each thread checks the logged vector clock against the current read count in the replay phase before a write event. We present an experiment and analyze the results using the Splash2x benchmark suite as well as two real-world applications. The experimental results show that on average, AggrePlay experiences a better reduction in compressed log size, and 56% better runtime slowdown during the record phase, as well as a 41.58% higher probability in the replay phase than existing work.
- Published
- 2019
34. Vorpal
- Author
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Joseph Izraelevitz, Jishen Zhao, Kunal Korgaonkar, and Steven Swanson
- Subjects
010302 applied physics ,Vector clock ,Computer science ,Serialization ,Distributed computing ,Control (management) ,Crash ,02 engineering and technology ,01 natural sciences ,020202 computer hardware & architecture ,Order (business) ,0103 physical sciences ,Scalability ,0202 electrical engineering, electronic engineering, information engineering - Abstract
In systems with non-volatile main memories (NVMMs), programmers must carefully control the order in which writes become persistent. Otherwise, what will remain in persistence after a crash may be unusable upon recovery. Prior art has already explored semantic models for specifying this persist order, but most enforcement algorithms for the order are not scalable to large server machines because they assume that the machine contains only one or two memory controllers. In this paper, we describe a collection of provably correct algorithms for enforcing the persist-order across writes, generated at many different cores, and persisted across numerous different memory controllers. Relative to existing solutions, our algorithms improve performance by 48% by reducing both traffic and serialization overheads.
- Published
- 2019
35. An Optimal Vector Clock Algorithm for Multithreaded Systems
- Author
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Vijay K. Garg and Xiong Zheng
- Subjects
Instruction set ,Debugging ,Vector clock ,Computer science ,Computation ,media_common.quotation_subject ,Bipartite graph ,Vertex cover ,Thread (computing) ,Timestamp ,Algorithm ,media_common - Abstract
Tracking causality (or happened-before relation) between events is useful for many applications such as debugging and recovery from failures. Consider a concurrent system with n threads and m objects. For such systems, either a vector clock of size n is used with one component per thread or a vector clock of size m is used with one component per object. A natural question is whether one can use a vector clock of size strictly less than the minimum of m and n to timestamp events. We give an algorithm in this paper that uses a hybrid of thread and object components. Our algorithm is guaranteed to return the minimum number of components necessary for vector clocks. We first consider the case when the interaction between objects and threads is statically known. This interaction is modeled by a thread-object bipartite graph. Our algorithm is based on finding the maximum bipartite matching of such a graph and then applying Konig-Egervary Theorem to compute the minimum vertex cover to determine the optimal number of components necessary for the vector clock. We also propose two mechanisms to compute such an vector clock when computation is revealed in an online fashion. Evaluation on different types of graphs indicates that our offline algorithm generates a size vector clock which is significantly less than the minimum of m and n. These mechanisms are more effective when the underlying bipartite graph is not dense.
- Published
- 2019
36. Practically-Self-stabilizing Vector Clocks in the Absence of Execution Fairness
- Author
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Iosif Salem and Elad Michael Schiller
- Subjects
Computer science ,Vector clock ,Transient (computer programming) ,Finite set ,Algorithm - Abstract
Vector clock algorithms are basic wait-free building blocks that facilitate causal ordering of events. As wait-free algorithms, they are guaranteed to complete their operations within a finite number of steps. Stabilizing algorithms allow the system to recover after the occurrence of transient faults, such as soft errors and arbitrary violations of the assumptions according to which the system was designed to behave.
- Published
- 2019
37. Optimized Sound and Complete Data Race Detection in Structured Parallel Programs
- Author
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Joshua Hooker, Kyle Storey, Peter Aldous, Eric Mercer, Jacob Powell, and Ben Ogles
- Subjects
Model checking ,Zipper ,Vector clock ,Computer science ,Serialization ,Transitive closure ,020207 software engineering ,02 engineering and technology ,Parallel computing ,Software_PROGRAMMINGTECHNIQUES ,Deadlock ,Task (computing) ,0202 electrical engineering, electronic engineering, information engineering ,020201 artificial intelligence & image processing ,Time complexity - Abstract
Task parallel programs that are free of data race are guaranteed to be deterministic, serializable, and free of deadlock. Techniques for verification of data race freedom vary in both accuracy and asymptotic complexity. One work is particularly well suited to task parallel programs with isolation and lightweight threads. It uses the Java Pathfinder model checker to reason about different schedules and proves the presence or absence of data race in a program on a fixed input. However, it uses a direct and inefficient transitive closure on the happens-before relation to reason about data race. This paper presents Zipper, an alternative to this naive algorithm, which identifies the presence or absence of data race in asymptotically superior time. Zipper is optimized for lightweight threads and, in the presence of many threads, has superior time complexity to leading vector clock algorithms. This paper includes an empirical study of Zipper and a comparison against the naive computation graph algorithm, demonstrating the superior performance it achieves.
- Published
- 2019
38. Ensuring Data Consistency
- Author
-
Andreas Meier and Michael Kaufmann
- Subjects
Atomicity ,Data consistency ,Theoretical computer science ,Computer science ,Relational database ,Vector clock ,NoSQL ,computer.software_genre ,Optimistic concurrency control ,computer ,Partition (database) ,CAP theorem - Abstract
Chapter 4 is the chapter of consistency concepts. First, the classical transactional concept of relational databases is given, including ACID (atomicity, consistency, isolation, and durability), followed by pessimistic and optimistic concurrency control mechanisms. Second, consistency issues of NoSQL databases are discussed such as the BASE (basically available, soft state, eventually consistent) concept and the CAP theorem (consistency, availability, and partition tolerance). In addition, vector clocks are introduced in order to serialize parallel transactions. A comparison between ACID and BASE closes the chapter.
- Published
- 2019
39. On the Growth of the Prime Numbers Based Encoded Vector Clock
- Author
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Ajay D. Kshemkalyani and Bhargav Voleti
- Subjects
Causality (physics) ,Consistency (database systems) ,Computer science ,Vector clock ,Encoding (memory) ,Scalability ,Process (computing) ,Prime number ,Scale (descriptive set theory) ,Algorithm - Abstract
The vector clock is a fundamental tool for tracking causality in parallel and distributed applications. Unfortunately, it does not scale well to large systems because each process needs to maintain a vector of size n, where n is the total number of processes in the system. To address this problem, the encoded vector clock (EVC) was recently proposed. The EVC is based on the encoding of the vector clock using prime numbers and uses a single number to represent vector time. The EVC has all the properties of the vector clock and yet uses a single number to represent global time. However, the single number EVC tends to grow fast and may soon exceed the size of the traditional vector clock. In this paper, we evaluate the growth rate of the size of the EVC using a simulation model. The simulations show that the EVC grows relatively fast, and the growth rate depends on the mix of internal events and communication events. To overcome this drawback, the EVC can be used in conjunction with several scalability techniques that can allow the use of the EVC in practical applications. We then present a case study of detecting memory consistency errors in MPI one-sided applications using EVC.
- Published
- 2018
40. Fully distributed clock synchronization in wireless sensor networks under exponential delays
- Author
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Yik-Chung Wu, Bin Luo, and Lei Cheng
- Subjects
0209 industrial biotechnology ,Linear programming ,Computer science ,Vector clock ,Computation ,020206 networking & telecommunications ,02 engineering and technology ,Clock synchronization ,Exponential function ,020901 industrial engineering & automation ,Control and Systems Engineering ,Control theory ,Signal Processing ,0202 electrical engineering, electronic engineering, information engineering ,Overhead (computing) ,Computer Vision and Pattern Recognition ,Self-clocking signal ,Electrical and Electronic Engineering ,Wireless sensor network ,Algorithm ,Software - Abstract
In this paper, we study the global clock synchronization problem for wireless sensor networks under unknown exponential delays in the two-way message exchange mechanism. The joint maximum likelihood estimator of clock offsets, clock skews and fixed delays for the network is formulated as a linear programming (LP) problem. Then, based on the alternating direction method of multipliers (ADMM), we propose a fully distributed synchronization algorithm which has low communication overhead and computation cost. Simulation results show that the proposed algorithm achieves better accuracy than consensus algorithm and the distributed least squares algorithm, and can always converge to the centralized optimal solution. HighlightsNetwork-wide clock synchronization problem under exponential message delays is solved.The problem is cast into a linear programming problem.ADMM is exploited to obtain a fully-distributed algorithm.Closed-from expressions are available for each update step in the algorithm.The proposed algorithm is guaranteed to converge to the global optimal solution.
- Published
- 2016
41. HEX: Scaling honeycombs is easier than scaling clock trees
- Author
-
Christoph Lenzen, Danny Dolev, Ulrich Schmid, Martin Perner, and Matthias Függer
- Subjects
Simulations ,Synchronous circuit ,Clock signal ,Computer science ,Vector clock ,Computer Networks and Communications ,Applied Mathematics ,Matrix clock ,Digital clock manager ,Parallel computing ,Clock skew ,Timing failure ,Theoretical Computer Science ,Computational Theory and Mathematics ,Asynchronous communication ,Clock distribution ,Skew analysis ,Byzantine fault-tolerance ,Self-stabilization - Abstract
We argue that grid structures are a very promising alternative to the standard approach for distributing a clock signal throughout VLSI circuits and other hardware devices. Traditionally, this is accomplished by a delay-balanced clock tree, which distributes the signal supplied by a single clock source via carefully engineered and buffered signal paths.Our approach, termed HEX, is based on a hexagonal grid with simple intermediate nodes, which both control the forwarding of clock ticks in the grid and supply them to nearby functional units. HEX is Byzantine fault-tolerant, in a way that scales with the grid size, self-stabilizing, and seamlessly integrates with multiple synchronized clock sources, as used in multi-synchronous Globally Synchronous Locally Asynchronous (GALS) architectures. Moreover, HEX guarantees a small clock skew between neighbors even for wire delays that are only moderately balanced. We provide both a theoretical analysis of the worst-case skew and simulation results that demonstrate very small typical skew in realistic runs.
- Published
- 2016
- Full Text
- View/download PDF
42. Scalability approaches for causal multicast: a survey
- Author
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Hendrik Decker, José Enrique Armendáriz-Iñigo, Rubén de Juan-Marín, Francesc D. Muñoz-Escoí, José M. Bernabéu-Aubán, Universidad Pública de Navarra. Departamento de Ingeniería Matemática e Informática, and Nafarroako Unibertsitate Publikoa. Matematika eta Informatika Ingeniaritza Saila
- Subjects
computer.internet_protocol ,Computer science ,Distributed computing ,Causal multicast ,02 engineering and technology ,Theoretical Computer Science ,Vector clock ,0202 electrical engineering, electronic engineering, information engineering ,Xcast ,Pragmatic General Multicast ,Numerical Analysis ,Protocol Independent Multicast ,Multicast ,business.industry ,Inter-domain ,Scalability ,020206 networking & telecommunications ,Multicast protocol ,Interconnection ,Computer Science Applications ,Computational Mathematics ,Source-specific multicast ,Computational Theory and Mathematics ,Reliable multicast ,IP multicast ,020201 artificial intelligence & image processing ,business ,LENGUAJES Y SISTEMAS INFORMATICOS ,computer ,Software ,Version vector ,Computer network - Abstract
Many distributed services need to be scalable: internet search, electronic commerce, e-government... In order to achieve scalability, high availability and fault tolerance, such applications rely on replicated components. Because of the dynamics of growth and volatility of customer markets, applications need to be hosted by adaptive, highly scalable systems. In particular, the scalability of the reliable multicast mechanisms used for supporting the consistency of replicas is of crucial importance. Reliable multicast might propagate updates in a pre-determined order (e.g., FIFO, total or causal). Since total order needs more communication rounds than causal order, the latter appears to be the preferable candidate for achieving multicast scalability, although the consistency guarantees based on causal order are weaker than those of total order. This paper provides a historical survey of different scalability approaches for reliable causal multicast protocols., This work was supported by European Regional Development Fund (FEDER) and Ministerio de Economia y Competitividad (MINECO) under research Grant TIN2012-37719-C03-01.
- Published
- 2015
43. Scalability approaches for causal multicast: a survey
- Author
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de Juan-Marín, Rubén, Decker, Hendrik, Armendáriz-Íñigo, José Enrique, Bernabéu-Aubán, José M., and Muñoz-Escoí, Francesc D.
- Published
- 2016
- Full Text
- View/download PDF
44. Ready, set, Go!
- Author
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Martin Steffen and Daniel Schnetzer Fava
- Subjects
Record locking ,Relation (database) ,Semantics (computer science) ,Programming language ,Computer science ,Vector clock ,Detector ,020207 software engineering ,Context (language use) ,02 engineering and technology ,computer.software_genre ,Set (abstract data type) ,020204 information systems ,Synchronization (computer science) ,0202 electrical engineering, electronic engineering, information engineering ,computer ,Software - Abstract
Data races are often discussed in the context of lock acquisition and release, with race-detection algorithms routinely relying on vector clocks as a means of capturing the relative ordering of events from different threads. In this paper, we present a data-race detector for a language with channel communication as its sole synchronization primitive, and provide a semantics directly tied to the happens-before relation, thus forging the notion of vector clocks.
- Published
- 2020
45. Two-Phase Dynamic Analysis of Message-Passing Go Programs Based on Vector Clocks
- Author
-
Kai Stadtmüller and Martin Sulzmann
- Subjects
Schedule (computer science) ,Relation (database) ,Computer science ,Programming language ,Vector clock ,Concurrency ,Message passing ,020207 software engineering ,02 engineering and technology ,Tracing ,computer.software_genre ,0202 electrical engineering, electronic engineering, information engineering ,020201 artificial intelligence & image processing ,Instrumentation (computer programming) ,computer ,TRACE (psycholinguistics) - Abstract
Understanding the runtime behavior of concurrent programs is a challenging task. A popular approach is to establish a happens-before relation via vector clocks. Thus, we can identify bugs and performance bottlenecks, for example, by checking if two conflicting events may happen concurrently. We employ a two-phase method to derive vector clock information for a wide range of concurrency features that includes all of the message-passing features in Go. The first phase (instrumentation and tracing) yields a runtime trace that records all events related to message-passing concurrency that took place. The second phase (trace replay) is carried out of fline and replays the recorded traces to infer vector clock information. Trace replay operates on thread-local traces. Thus, we can observe behavior that might result from some alternative schedule. Our approach is not tied to any specific language. We have built a prototype for the Go programming language and provide empirical evidence of the usefulness of our method.
- Published
- 2018
46. Nemo
- Author
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Sebastiano Peluso, Masoomeh Javidi Kishi, Ahmed Hassan, Mohamed Mohamedin, and Roberto Palmieri
- Subjects
020203 distributed computing ,Hardware_MEMORYSTRUCTURES ,Computer science ,Vector clock ,Transactional memory ,020207 software engineering ,02 engineering and technology ,Thread (computing) ,computer.software_genre ,Concurrency control ,Scalability ,0202 electrical engineering, electronic engineering, information engineering ,Operating system ,Online transaction processing ,Timestamp ,computer - Abstract
In this paper we present Nemo, a NUMA-aware Transactional Memory (TM) design and implementation optimized for promoting scalability in applications running on top of NUMA architectures. Nemo deploys a hybrid design where conflicting threads alternate the usage of single timestamps and vector clocks to identify inconsistent executions depending upon the source of conflict. We assessed the performance of Nemo by using both synthetic and well-known OLTP transactional workloads. Our approach offers improvements over the six state-of-the-art competitors we implemented.
- Published
- 2018
47. Toward a Uniform Approach to the Unfolding of Nets
- Author
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G. Michele Pinna, Eric Fabre, SUpervision of large MOdular and distributed systems (SUMO), Inria Rennes – Bretagne Atlantique, Institut National de Recherche en Informatique et en Automatique (Inria)-Institut National de Recherche en Informatique et en Automatique (Inria)-LANGAGE ET GÉNIE LOGICIEL (IRISA-D4), Institut de Recherche en Informatique et Systèmes Aléatoires (IRISA), Université de Bretagne Sud (UBS)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut National des Sciences Appliquées (INSA)-Université de Rennes (UNIV-RENNES)-Institut National des Sciences Appliquées (INSA)-Université de Rennes (UNIV-RENNES)-Institut National de Recherche en Informatique et en Automatique (Inria)-École normale supérieure - Rennes (ENS Rennes)-Centre National de la Recherche Scientifique (CNRS)-Université de Rennes 1 (UR1), Université de Rennes (UNIV-RENNES)-CentraleSupélec-IMT Atlantique Bretagne-Pays de la Loire (IMT Atlantique), Institut Mines-Télécom [Paris] (IMT)-Institut Mines-Télécom [Paris] (IMT)-Université de Bretagne Sud (UBS)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut Mines-Télécom [Paris] (IMT)-Institut Mines-Télécom [Paris] (IMT)-Institut de Recherche en Informatique et Systèmes Aléatoires (IRISA), Institut National des Sciences Appliquées (INSA)-Université de Rennes (UNIV-RENNES)-Institut National des Sciences Appliquées (INSA)-Université de Rennes (UNIV-RENNES)-École normale supérieure - Rennes (ENS Rennes)-Centre National de la Recherche Scientifique (CNRS)-Université de Rennes 1 (UR1), Institut Mines-Télécom [Paris] (IMT)-Institut Mines-Télécom [Paris] (IMT), Universita degli Studi di Cagliari [Cagliari], Université de Rennes (UR)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Université de Bretagne Sud (UBS)-École normale supérieure - Rennes (ENS Rennes)-Institut National de Recherche en Informatique et en Automatique (Inria)-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS)-IMT Atlantique (IMT Atlantique), Institut Mines-Télécom [Paris] (IMT)-Institut Mines-Télécom [Paris] (IMT)-Université de Rennes (UR)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Université de Bretagne Sud (UBS)-École normale supérieure - Rennes (ENS Rennes)-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS)-IMT Atlantique (IMT Atlantique), and Università degli Studi di Cagliari = University of Cagliari (UniCa)
- Subjects
FOS: Computer and information sciences ,Computer Science - Logic in Computer Science ,Theoretical computer science ,Computer science ,Concurrency ,0102 computer and information sciences ,02 engineering and technology ,Trellis (graph) ,[INFO.INFO-SE]Computer Science [cs]/Software Engineering [cs.SE] ,01 natural sciences ,lcsh:QA75.5-76.95 ,020204 information systems ,0202 electrical engineering, electronic engineering, information engineering ,Hardware_INTEGRATEDCIRCUITS ,Concurrency semantics ,[INFO]Computer Science [cs] ,Vector clock ,lcsh:Mathematics ,F 1.1 ,Contrast (statistics) ,Petri net ,lcsh:QA1-939 ,Net (mathematics) ,Logic in Computer Science (cs.LO) ,Computer Science - Distributed, Parallel, and Cluster Computing ,010201 computation theory & mathematics ,Distributed, Parallel, and Cluster Computing (cs.DC) ,lcsh:Electronic computers. Computer science - Abstract
In this paper we introduce the notion of spread net. Spread nets are (safe) Petri nets equipped with vector clocks on places and with ticking functions on transitions, and are such that vector clocks are consistent with the ticking of transitions. Such nets generalize previous families of nets like unfoldings, merged processes and trellis processes, and can thus be used to represent runs of a net in a true concurrency semantics through an operation called the spreading of a net. By contrast with previous constructions, which may identify conflicts, spread nets allow loops in time, In Proceedings ICE 2018, arXiv:1810.02053
- Published
- 2018
48. Thread-local concurrency
- Author
-
Dong H. Ahn, Joachim Protze, Matthias S. Müller, and Martin Schulz
- Subjects
Novel technique ,POSIX Threads ,Computer science ,Vector clock ,Programming language ,Concurrency ,020206 networking & telecommunications ,02 engineering and technology ,Thread (computing) ,Spotting ,computer.software_genre ,0202 electrical engineering, electronic engineering, information engineering ,Programming paradigm ,020201 artificial intelligence & image processing ,computer - Abstract
With greater adoption of various high-level parallel programming models to harness on-node parallelism, accurate data race detection has become more crucial than ever. However, existing tools have great difficulty spotting data races through these high-level models, as they primarily target low-level concurrent execution models (e.g., concurrency expressed at the level of POSIX threads). In this paper, we propose a novel technique to accurately detect those data races that can occur at higher levels of concurrent execution. The core idea of our technique is to introduce the general concept of Thread-Local Concurrency (TLC) as a new way to translate the concurrency expressed by a high-level programming paradigm into the low execution level understood by the existing tools. Specifically, we extend the definition of vector clocks to allow the existing state-of-the-art race detectors to recognize those races that occur at the higher level of concurrency with minor modifications to these tools. Our evaluation with our prototype implemented within ThreadSanitizer shows that TLC can allow the existing tool to detect these races accurately with only small additional analysis overheads.
- Published
- 2018
49. Distributed computation of vector clocks in Petri nets unfolding for test selection
- Author
-
Stefan Schwoon, Agnes Madalinski, Loïg Jezequel, Laboratoire des Sciences du Numérique de Nantes (LS2N), IMT Atlantique Bretagne-Pays de la Loire (IMT Atlantique), Institut Mines-Télécom [Paris] (IMT)-Institut Mines-Télécom [Paris] (IMT)-Université de Nantes - UFR des Sciences et des Techniques (UN UFR ST), Université de Nantes (UN)-Université de Nantes (UN)-École Centrale de Nantes (ECN)-Centre National de la Recherche Scientifique (CNRS), Université de Nantes (UN), Otto-von-Guericke University [Magdeburg] (OVGU), Modeling and Exploitation of Interaction and Concurrency (MEXICO), Laboratoire Spécification et Vérification [Cachan] (LSV), École normale supérieure - Cachan (ENS Cachan)-Centre National de la Recherche Scientifique (CNRS)-École normale supérieure - Cachan (ENS Cachan)-Centre National de la Recherche Scientifique (CNRS)-Inria Saclay - Ile de France, Institut National de Recherche en Informatique et en Automatique (Inria)-Institut National de Recherche en Informatique et en Automatique (Inria), École normale supérieure - Cachan (ENS Cachan)-Centre National de la Recherche Scientifique (CNRS), Université de Nantes - UFR des Sciences et des Techniques (UN UFR ST), Université de Nantes (UN)-Université de Nantes (UN)-École Centrale de Nantes (ECN)-Centre National de la Recherche Scientifique (CNRS)-IMT Atlantique (IMT Atlantique), Institut Mines-Télécom [Paris] (IMT)-Institut Mines-Télécom [Paris] (IMT), Otto-von-Guericke-Universität Magdeburg = Otto-von-Guericke University [Magdeburg] (OVGU), and Université de Nantes (UN)-Université de Nantes (UN)-École Centrale de Nantes (ECN)-Centre National de la Recherche Scientifique (CNRS)-IMT Atlantique Bretagne-Pays de la Loire (IMT Atlantique)
- Subjects
0209 industrial biotechnology ,Computer science ,Vector clock ,Distributed computing ,Computation ,02 engineering and technology ,Petri net ,Task (project management) ,020901 industrial engineering & automation ,Control and Systems Engineering ,Order (business) ,TheoryofComputation_LOGICSANDMEANINGSOFPROGRAMS ,0202 electrical engineering, electronic engineering, information engineering ,020201 artificial intelligence & image processing ,Test selection ,[INFO]Computer Science [cs] - Abstract
International audience; It has been shown that annotating Petri net unfoldings with time stamps allows for building distributed testers for distributed systems. However, the construction of the annotated unfolding of a distributed system currently remains a centralized task. In this paper we extend a distributed unfolding technique in order to annotate the resulting unfolding with time stamps. This allows for distributed construction of distributed testers for distributed systems.
- Published
- 2018
50. Encoded Vector Clock
- Author
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Ajay D. Kshemkalyani, Ashfaq Khokhar, and Min Shen
- Subjects
Computer science ,Vector clock ,Distributed computing ,Process (computing) ,Prime number ,020206 networking & telecommunications ,Scale (descriptive set theory) ,0102 computer and information sciences ,02 engineering and technology ,01 natural sciences ,Causality (physics) ,010201 computation theory & mathematics ,Encoding (memory) ,Scalability ,0202 electrical engineering, electronic engineering, information engineering ,Timestamp - Abstract
The vector clock is a fundamental tool for tracking causality in distributed applications. Unfortunately, it does not scale well to large systems because each process needs to maintain a vector of size n, where n is the total number of processes in the system. To address this problem, we propose the encoding of the vector clock using prime numbers to use a single number to represent vector time. We propose the operations on the encoded vector clock (EVC). We then show how to timestamp global states and how to perform operations on the global states using the EVC. We also discuss scalability issues of the EVC.
- Published
- 2018
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