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Distributed large memory offers the use of large virtual memory by using remote memory distributed over nodes in a cluster. The message passing interface (MPI) plays important role in DLM. MPI-based DLM manages the large virtual memory over the cluster using MPI batch queuing system. In Distributed memory system message MPI is important parallel programming. As the number of virtual machines increases MPI and shared memory parallel programming combined to perform efficient communication in virtual machines [1,2]. Various tasks communicate with each other by sharing memory on the different disk through shared memory distributed computing. If various tasks are trying to access same the same memory location for reading and writing purpose, sometimes it may cause deadlock. In this case synchronization mechanism should handle such situation to keep the integrity of the data [2]. MapReduce and Hadoop are having inbuilt functions to handle distributed shared memory mechanism. The distributed computing with MPI can process thousands of parallel processes in cloud environment [ABSTRACT FROM AUTHOR]

Abstract Background Unlike conventional T cells, innate and virtual-memory CD8 T cells in naïve mice acquire their memory phenotypes and functions in the absence of antigenic encounters in a cytokine-dependent manner. The relevant cytokines include interleukin-4 (IL-4), type I interferon, and interleukin-15 (IL-15). Moreover, exogenous IL-4 can also induce de novo generation and/or expansion of the virtual-memory CD8 T cell population. In this study, we investigated whether exogenous IL-4 could enhance the immune response to a viral infection. Results In vivo administration of IL-4 and an anti-IL-4 antibody complex (IL-4C) increased CXCR3 expression in both memory and naïve phenotype CD8 T cells in the absence of antigenic stimulation, and protected mice from lethal influenza infection. Flow cytometric analysis of lung-infiltrating immune cells on day 5 after virus infection revealed higher numbers of antigen-specific and bystander CD8 T cells in IL-4C-treated mice than in control mice. In particular, the bystander CD8 T cells were a naïve or evident memory phenotypes. Crucially, an anti-CXCR3 blocking antibody abrogated this IL-4C effect, reflecting that the increased accumulation of CD8 T cells in the lungs after IL-4C treatment is dependent on CXCR3. Conclusions These data demonstrate that exogenous IL-4C plays a protective role by enhancing CXCR3-dependent migration of CD8 T cells into influenza-infected lungs.

Background: Unlike conventional T cells, innate and virtual-memory CD8 T cells in naïve mice acquire their memory phenotypes and functions in the absence of antigenic encounters in a cytokine-dependent manner. The relevant cytokines include interleukin-4 (IL-4), type I interferon, and interleukin-15 (IL-15). Moreover, exogenous IL-4 can also induce de novo generation and/or expansion of the virtual-memory CD8 T cell population. In this study, we investigated whether exogenous IL-4 could enhance the immune response to a viral infection. Results: In vivo administration of IL-4 and an anti-IL-4 antibody complex (IL-4C) increased CXCR3 expression in both memory and naïve phenotype CD8 T cells in the absence of antigenic stimulation, and protected mice from lethal influenza infection. Flow cytometric analysis of lung-infiltrating immune cells on day 5 after virus infection revealed higher numbers of antigen-specific and bystander CD8 T cells in IL-4C-treated mice than in control mice. In particular, the bystander CD8 T cells were a naïve or evident memory phenotypes. Crucially, an anti-CXCR3 blocking antibody abrogated this IL-4C effect, reflecting that the increased accumulation of CD8 T cells in the lungs after IL-4C treatment is dependent on CXCR3. Conclusions: These data demonstrate that exogenous IL-4C plays a protective role by enhancing CXCR3-dependent migration of CD8 T cells into influenza-infected lungs. [ABSTRACT FROM AUTHOR]

A crucial design factor for users of smart mobile devices is the latency of graphical interface interaction. Switching a background app to foreground is a frequent operation on mobile devices and the latency of this process is highly perceivable to users. Based on an Android smartphone, through analysis of memory reference generated during the app-switching process, we observe that file (virtual) pages and anonymous pages are both heavily involved. However, to our surprise, the amounts of the two types of pages in the main memory are highly imbalanced, and frequent I/O operations on file pages noticeably slows down the appswitching process. In this study, we advocate to improve the app-switching latency by rectifying the skewed kernel page reclaiming.Our approach involves two parts: proactive identification of unused anonymous pages and adaptive balance between file pages and anonymous pages. As mobile apps are found inflating their anonymous pages, we propose identifying unused anonymous pages in sync with the app-switching events. In addition, Android devices replaces the swap device with RAM-based zram, and swapping on zram is much faster than file accessing on flash storage. Without causing thrashing, we propose swapping out as many anonymous pages to zram as possible for caching more file pages.We conduct experiments on a Google Pixel phone with realistic user workloads, and results confirm that our method is adaptive to different memory requirements and greatly improves the app-switching latency by up to 43% compared with the original kernel. [ABSTRACT FROM AUTHOR]

The general-purpose virtual-memory subsystem of Linux does not scale to the multimillion IOP/s SSDs of today. Further, its implicit write-back and back-fill semantic hinders data-intensive applications, like databases, more than it actually helps. In contrast, explicit virtual-memory abstractions, as introduced by ExMap, provide an Exokernel-like interface to manipulate theVMsurface. Thereby, the user application remains in full control over the VM surface and can benefit from low operation latencies. In this paper, we investigate the performance of the existing ExMap abstraction and propose enhancements for its system-call interface, its process-local memory pool management, and the user-space page-state tracking. With memory-mapped I/O vectors, the global bundle list, and exported page tables, we improve the end-toend throughput of in-memory random B+tree lookups by up to 5.7 percent, while the out-of-memory case improves by up to 4.9 percent.

As the memory footprint of emerging applications continues to increase, the address translation becomes a critical performance bottleneck owing to frequent misses on the Translation Lookaside Buffer (TLB). In addition, the TLB miss penalty becomes more critical in modern computer systems because the levels of the hierarchical page table (a.k.a. radix page table) are increasing to extend the address space. To reduce TLB misses, modern high-performance processors employ a multi-level TLB structure using a large last-level TLB. Employing a large last-level TLB may reduce TLB misses. However, its capacity is still limited, and it can incur a chip area overhead. In this paper, we propose a Page Structure Entry (PSE) pinning mechanism that provides a large PSE store by dedicating some space to the last-level cache to store only the page structure entries. The PSE Pinning is based on three key observations. First, memory-intensive applications suffer from frequent misses in the last-level cache. Thus, most of the space in the last-level cache is not utilized well. Second, most PSEs are fetched from the main memory during the page table walk process, meaning that the cache lines for the PSEs are frequently evicted from on-chip caches. Finally, a small number of PSEs are frequently accessed while others are not. By exploiting these three observations, PSE Pinning pins the frequently accessed page structure entries to the last-level caches so that they can reside on the cache. Experimental results show that PSE Pinning improves the performance of memory-intensive workloads suffering from frequent L2 TLB misses by 7.8% on average.

Antigen-inexperienced memory-phenotype CD8+ T cells are categorized as innate memory cells in the thymus or virtual memory (VM) CD8+ T cells in peripheral tissues. The key distinction between these cell types is their differing responses to IL-4, but the minimal effect of IL-4 on VM CD8+ T cell expansion in the periphery is not well understood. To address this, we investigated the development of VM CD8+ T cells in the periphery of IL-4 knockout (KO) C57BL/6 mouse. CD8+ splenocytes were isolated from the spleen of wilt-type (WT) and IL-4 KO mice, followed by single-cell RNA sequencing and Seurat analysis on sorted CD8+ cells using the 10x Genomics platform. This study identified various CD8+ T cell subtypes, including naïve, effector, IFN-stimulated, true memory (TM), and VM T cells. VM CD8+ T cells were characterized by high expression of Cd44 , Cxcr3 , Il2rb , Eomes , Tbx21 , Ly6c2 , and low expression of Itga4. In IL-4-deficient mouse, macrophages were significantly reduced, while memory T cell populations showed a slight increase compared to WT mouse. Both Itga4 + TM and Itga4 - VM CD8+ T cells were more abundant in IL-4 KO mouse. Within the VM T cell group, Ly6a − VM CD8+ T cells were reduced, while Ly6a + VM CD8+ T cells were increased relative to WT mouse. These Ly6a + VM CD8+ cells exhibited high expression of genes linked to type I IFN signaling, such as Isg15, Ifit1, and Stat1. Our findings suggest that IFN-influenced Ly6a + VM CD8+ T cells play a role in maintaining the peripheral VM CD8+ T cell population in the absence of IL-4. • VM CD8+ T cells are characterized by high expression of Cd44 , Cxcr3 , Il2rb , Eomes , Tbx21 , Ly6c2 , and low expression of Itga4. • The Ly6a + VM T cell subset, with high type I IFN signaling gene expression, expands in IL-4 deficient conditions compared to WT mouse. • Homeostasis of the peripheral VM T cell pool in IL-4 deficiency can be compensated by the influence of type I IFN. [ABSTRACT FROM AUTHOR]

While observing various situations and experiences, imagination institutes new realities within the distinctions between the animate and the inanimate, whose relations no longer reflect the customary order of the material world. That is why it makes sense to explore the emerging systems, in which new modes of participation and self-organisation that are capable of changing the definitions of life are formed. If we choose the distortion of the experienced time as the observation method, a moving image can be used for that purpose. The author of the article suggests understanding animation as changes in the state of systems when time perception is manipulated (e.g., the time-lapse technique in photography/video). By problematizing the understanding of animation, the author offers to explore it in two directions – on the material level, when animation is happening through constant agreements between the animate and the inanimate, and on the level of animation instituted as a cultural construct. Thus, the concept of animation is construed as immanent to culture – cinema, memory culture, philosophy of time and, alongside, as animation of matter, in which the systems coming into agreement institute the shapes of common consciousness (bioanimation, consciousness animation). The system perceiving itself as human tries to establish possible interactions with other systems through requests, which can be considered animation. Alongside, the term of animability is offered, which defines the capacity of matter to take part in such human/inhuman relations. The immersive state that appears in the process of animation as an unending “immersing” into virtual reality is discussed. In this text that does not have illustrations, the author invites us to feel images as possible human/inhuman assemblages and to predict possible life forms by manipulating the expressions of time and thus creating agreed realities. It is asserted in the article that animation is a request sent by certain forms of matter to other forms, thus creating agreed systems that organize various shapes of consciousness as constitutions uniting these systems. The author tries to assemble into a constellation several important positions – memory (the courage of vision, an expression of time), catastrophe (the separation of testimony, rhythm, a possibility of a memory echo), vibrating matter (in a ready state) and virtual reality (reality augmented with visions of matter). [ABSTRACT FROM AUTHOR]

The first step required to perform any analysis of a physicalmemory image is the reconstruction of the virtual address spaces, which allows translating virtual addresses to their corresponding physical offsets. However, this phase is often overlooked, and the challenges related to it are rarely discussed in the literature. Practical tools solve the problem by using a set of custom heuristics tailored on a very small number of well-known operating systems (OSs) running on few architectures. In this article, we look for the first time at all the different ways the virtual to physical translation can be operated in 10 different CPU architectures. In each case, we study the inviolable constraints imposed by the memory management unit that can be used to build signatures to recover the required data structures from memory without any knowledge about the running OS. We build a proof-of-concept tool to experiment with the extraction of virtual address spaces showing the challenges of performing an OS-agnostic virtual to physical address translation in real-world scenarios. We conduct experiments on a large set of 26 different OSs and a use case on a real hardware device. Finally, we show a possible usage of our technique to retrieve information about user space processes running on an unknown OS without any knowledge of its internals. [ABSTRACT FROM AUTHOR]

It is widely accepted that central and effector memory CD4+ T cells originate from naïve T cells after they have encountered their cognate antigen in the setting of appropriate co-stimulation. However, if this were true the diversity of T cell receptor (TCR) sequences within the naïve T cell compartment should be far greater than that of the memory T cell compartment, which is not supported by TCR sequencing data. Here we demonstrate that aged mice with far fewer naïve T cells, respond to the model antigen, hen eggwhite lysozyme (HEL), by utilizing the same TCR sequence as their younger counterparts. CD4+ T cell repertoire analysis of highly purified T cell populations from naive animals revealed that the HEL-specific clones displayed effector and central "memory" cell surface phenotypes even prior to having encountered their cognate antigen. Furthermore, HEL-inexperienced CD4+ T cells were found to reside within the naïve, regulatory, central memory, and effector memory T cell populations at similar frequencies and the majority of the CD4+ T cells within the regulatory and memory populations were unexpanded. These findings support a new paradigm for CD4+ T cell maturation in which a specific clone can undergo a differentiation process to exhibit a "memory" or regulatory phenotype without having undergone a clonal expansion event. It also demonstrates that a foreign-specific T cell is just as likely to reside within the regulatory T cell compartment as it would the naïve compartment, arguing against the specificity of the regulatory T cell compartment being skewed towards self-reactive T cell clones. Finally, we demonstrate that the same set of foreign and autoreactive CD4+ T cell clones are repetitively generated throughout adulthood. The latter observation argues against T cell-depleting strategies or autologous stem cell transplantation as therapies for autoimmunity-as the immune system has the ability to regenerate pathogenic clones.

Due to the ongoing slowdown of Dennard scaling, heterogeneous hardware architectures are inevitable to meet the increasing demand for energy efficient systems. However, one of the most important aspects that shape today’s computing landscape is the wide availability of software that can run on any system. Current applications that use accelerators, in contrast, are often especially tailored to a specific hardware setup and therefore not universally deployable. This is particularly true for reconfigurable logic as their internal structure requires the circuits and their integration to be designed as well. This makes them inherently difficult to use and therefore less accessible for a general audience. Nevertheless, their balance of flexibility and efficiency puts reconfigurable accelerators in a unique position between CPUs, GPUs, and ASICs. Therefore, one of the main challenges of future heterogeneous systems is to foster collaborative computing between these vastly different components while still being simple to use. Previous approaches mostly focused on subproblems instead of a holistic view of hardware and software in the context of commonplace usability. This paper analyzes the general demands on a reconfigurable platform and derives their requirements regarding accessibility and security. Hereby, we investigate several key features like hardware virtualization, system shared virtual memory, and the use of wide-spread programming paradigms. Then, we systematically build up such a platform based on the established ROCm GPU framework and its internal HSA standard. This new common HERA methodology is finally also demonstrated as a prototype.

The working set model for program behavior was invented in 1965. It has stood the test of time in virtual memory management for over 50 years. It is considered the ideal for managing memory in operating systems and caches. Its superior performance was based on the principle of locality, which was discovered at the same time; locality is the observed tendency of programs to use distinct subsets of their pages over extended periods of time. This tutorial traces the development of working set theory from its origins to the present day. We will discuss the principle of locality and its experimental verification. We will show why working set memory management resists thrashing and generates near-optimal system throughput. We will present the powerful, linear-time algorithms for computing working set statistics and applying them to the design of memory systems. We will debunk several myths about locality and the performance of memory systems. We will conclude with a discussion of the application of the working set model in parallel systems, modern shared CPU caches, network edge caches, and inventory and logistics management. [ABSTRACT FROM AUTHOR]

Conventional CD8+ memory T cells develop upon stimulation with foreign antigen and provide increased protection upon re-challenge. Over the past two decades, new subsets of CD8+ T cells have been identified that acquire memory features independently of antigen exposure. These antigen-inexperienced memory T cells (TAIM) are described under several names including innate memory, virtual memory, and memory phenotype. TAIM cells exhibit characteristics of conventional or true memory cells, including antigen-specific responses. In addition, they show responsiveness to innate stimuli and have been suggested to provide additional levels of protection toward infections and cancer. Here, we discuss the current understanding of TAIM cells, focusing on extrinsic and intrinsic molecular conditions that favor their development, their molecular definitions and immunological properties, as well as their transcriptional and epigenetic regulation. [ABSTRACT FROM AUTHOR]

Superpages have long been proposed to enlarge the coverage of translation lookaside buffer (TLB). They are extremely beneficial for reducing address translation overhead in big memory systems, such as hybrid memory systems that composed of DRAM and non-volatile memories (NVMs). However, superpages conflict with fine-grained memory migration, one of the key techniques in hybrid memory systems to improve performance and energy efficiency. Fine-grained page migrations usually require to splinter superpages, mitigating the benefit of TLB hardware for superpages. In this paper, we present Tamp, an efficient memory management mechanism to support multiple page sizes in hybrid memory systems. We manage large-capacity NVM using superpages, and use a relatively small size of DRAM to cache hot base pages within the superpages. We find that there are remarkable contiguity exist for hot base pages in superpages. In response, we bind those contiguous hot pages together and migrate them to DRAM. We also propose multi-grained TLBs to coalesce multiple page address translations into a single TLB entry. Our experimental results show that Tamp can significantly reduce TLB misses by 62.4% on average, and improve application performance (IPC) by 16.2%, compared to a page migration policy without TLB coalescing support.

This paper focuses on the Translation Lookaside Buffer (TLB) management as part of memory management. TLB is an associative cache of the advanced processors, which reduces the overhead of the virtual to physical address translations. We consider challenges related to the design of the TLB management subsystem of the OS kernel on the example of the IA-32 platform and propose a simple model of complete and consistent policy of TLB management. This model can be used as a foundation for memory management subsystems design and verification.

This report introduces the M-M/S-CD memory management model which was designed for true microkernels as an alternative to capability-based memory management. The proposed model is more simple in design and implementation and provides more power and flexibility to the user mode memory management servers. In the same time it maintains consistency of memory layout and enforces strict and clear memory isolation/sharing rules, creating stable environment for applications.

The emerging non-volatile memory ( NVM) is byte-addressable, which has the characteristics of low latency similar to memory and the nonvolatile property of storage. Limited by the maturity of hardware and software technology, NVM was firstly used in storage. This paper discussed a series of problems and management challenges of NVM for storage. Then, it summarized the main features of the existing typical NVM file systems. These features mainly focused on reducing consistency overhead, reducing the software stack cost, the integrated management of memory and storage, distributed file system, NVM file system security, fault tolerance, space management and so on. Finally, this paper prospected several research directions of NVM file system, including scalability, fusion of virtual memory and file system, and distributed file system. [ABSTRACT FROM AUTHOR]

Objectives: With the increasing demand of digital map and geographic information service, the rapid and efficient cartographic and geo‐information updating technology is urgently needed. Collaborative mapping is an effective way to improve the efficiency of cartography for rapidly updating map products and geospatial database.Methods: Considering the low efficiency of collaborative mapping transaction execution and the complexity of transaction concurrency control, we propose a map editing transaction model simulated by map document status change. The proposed model supports spatial coordinates, attributes, graphics, and relation definition, and it also describes map editing transactions by simulating the change of map document status. Map document data backups and data changes are used to store and organize map editing transactions. This paper provides a high efficiency editing transaction processing method for collaborative mapping. Results: Experiments show that the model makes the map editing process work without the limitation of execution efficiency in database management system (DBMS), and strictly maintains the characteristics of atomicity, consistency, isolation and durability in map editing transactions.Conclusions: The synchronous display of collaborative mapping users' map views can be well supported, and all users in the collaborative working group can see the same map content. Compared with the map database based on DBMS, the proposed method has higher execution efficiency and transaction management capability, and can be used for rapid updating of geospatial database and cartographic database. [ABSTRACT FROM AUTHOR]

We present the methodology, as well as results of measurements and evaluation of overhead created by concurrency and virtual memory. A special measurement technique and testbed were used to obtain the most accurate data from the experiments. This technique is focused on the measurements of the overall performance degradation that is introduced by concurrency in the form of lightweight user-level threads on IA-32 processors. We have obtained and compared results of the experiments in an environment with and without enabled virtual memory to understand what loss of performance is caused by virtual memory in itself, and how it affects the overhead associated with concurrency. The results showed that overhead of concurrency outweighs virtual memory overhead and that there is a complex dependency between them. The article is published in the author’s wording.

It has been appreciated for more than three decades that the interactions between the T‐cell antigen receptor and self‐antigens are the major determinants of the cell fates of developing thymocytes and the establishment of central tolerance. However, recent evidence shows that the level of self‐reactivity substantially contributes to fate choices of positively selected mature T cells in homeostasis, as well as during immune responses. This implies that individual clones of peripheral T cells are predisposed to specific functional properties based on the self‐reactivity of their antigen receptors. Overall, the relative difference in the self‐reactivity among peripheral T cells is an important factor contributing to the diversity of T‐cell responses to foreign antigens. [ABSTRACT FROM AUTHOR]

Cytotoxic T cell differentiation is guided by epigenome adaptations, but how epigenetic mechanisms control lymphocyte development has not been well defined. Here we show that the histone methyltransferase DOT1L, which marks the nucleosome core on active genes, safeguards normal differentiation of CD8+ T cells. T cell-specific ablation of Dot1L resulted in loss of naïve CD8+ T cells and premature differentiation toward a memory-like state, independent of antigen exposure and in a cell-intrinsic manner. Mechanistically, DOT1L controlled CD8+ T cell differentiation by ensuring normal T cell receptor density and signaling. DOT1L also maintained epigenetic identity, in part by indirectly supporting the repression of developmentally regulated genes. Finally, deletion of Dot1L in T cells resulted in an impaired immune response. Through our study, DOT1L is emerging as a central player in physiology of CD8+ T cells, acting as a barrier to prevent premature differentiation and controlling epigenetic integrity. [ABSTRACT FROM AUTHOR]

Swap space in Linux is used when the amount of physical memory (RAM) is full. If the system needs more memory resources and the RAM is full, inactive pages in memory are moved to the swap space. While swap space can help machines with a small amount of RAM, it should not be considered a replacement for more RAM. Swap space is located on hard drives, which have a slower access time than physical memory. If any memory-intensive application is deployed on a PC with limited amount of Random-Access Memory, the inactive (not recently used) application which is generally the system UI is shifted to the Swap memory (much slower than RAM). This makes the entire UI slow but the higher priority processes (the most recent applications) remain unaffected because they remain in the RAM. When we are finished with our work with the memory intensive application and close it, the RAM gets cleared and has ample of space to accommodate the contents of the SWAP memory. But the swap memory stays as it is, and does not get transferred back to the RAM. This results in slower UI even though the system has enough RAM and no memory intensive process is running. This then results in lag in UI transition, delayed application launches, slower processing of programs and a large overhead.In years past, the recommended amount of swap space increased linearly with the amount of RAM in the system. But because the amount of memory in modern systems has increased into the hundreds of gigabytes, it is now recognized that the amount of swap space that a system needs is a function of the memory workload running on that system.In the world of enhanced hardware and superior machines, the software enhancements and optimization for low end PC's is sometimes neglected. Hence, we propose a technique to overcome the lag created by the swap space y moving the content of the swap memory back to the RAM and a total boost is provided to the system. The technique is evaluated under various configurations and proves to solve the problem. [ABSTRACT FROM AUTHOR]

In this paper we present a tool that virtualizes creation and execution of large address space programs, and visualizes working of virtual memory system in response to their virtualized execution to facilitate effective teaching–learning of the abstract concept and technical details of virtual memory system. The tool allows users to write large address space virtual programs using a small set of instructions, virtualize their execution and visualize the working of virtual memory system in response to their virtualized execution. We also evaluated students' response towards the tool to investigate its teaching–learning effectiveness and acceptance by student community. The results suggest that with respect to the Technology Acceptance Model variables, students had positive values indicating a tendency to be favorable towards using the tool in their learning. Students exhibited high intention to use the tool, demonstrated a high positive attitude towards the tool, and showed high perceived usefulness of the tool to acquire complete, concrete and confident knowledge of virtual memory system. [ABSTRACT FROM AUTHOR]

Immunological memory is a phenomenon where the immune system can respond more rapidly to pathogens and immunological challenges that it has previously encountered. It is defined by several key hallmarks. After an initial encounter, immune cells (1) expand and (2) differentiate to form memory cell populations. Memory cells are (3) long‐lived and (4) facilitate more rapid immune responses to subsequent infection because of (i) an increase in cell number, (ii) a decrease in the signaling threshold required for entry into cell cycle or effector function and (iii) localization of cells to tissue sites for surveillance. Classically, immunological memory has been antigen specific but it is becoming apparent that mechanisms of immunological memory can be co‐opted by innate or antigen‐inexperienced immune cells to generate heterogeneity in immune responses. One such cell is the virtual memory CD8 T (TVM) cell, which is a semi‐differentiated but antigen‐naïve CD8 T‐cell population. This review will summarize current knowledge of how TVM cells are generated, their memory‐like hallmarks, how they are maintained during steady state, infection and aging, and propose a model to integrate key signaling pathways during their generation. [ABSTRACT FROM AUTHOR]