44 results on '"Yang, Tahone"'
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2. PMOS junction optimization for 3D NAND FLASH memory with CMOS under array
3. A Case of Plasma-Induced Film Breakdown in 3D NAND BEOL Dielectric Etch
4. The Constraint Artificial-Intelligence Assisted Method for Etching Structure Optimization
5. Improvement of cell reliability by floating gate implantation on 1Xnm NAND flash memory
6. Properties of N-rich Silicon Nitride Film Deposited by Plasma-Enhanced Atomic Layer Deposition
7. Post-Etch Yield Killer Defects in 3D NAND High Aspect Ratio Etching Process
8. Common Source Line-to-Word Line Short Improvement by Eliminating SLT Sidewall Notch in 3D NAND Deep Trench Patterning
9. Machine learning Assists on High Aspect Ratio Slit Trench Etching in 3D NAND
10. Improvement of Twisting and Line-Edge Roughness of 3D NAND Deep Trench Etching on Yield Enhancement : AEPM: Advanced Equipment Processes and Materials
11. Improvement of Multi-Lines Bridge Defect Classification by Hierarchical Architecture in Artificial Intelligence Automatic Defect Classification
12. CMP Process Optimization Engineering by Machine Learning
13. CMP Process Optimization Engineering by Machine Learning
14. Study of Plasma Ash Rate Enhancement by Machine Learning Models for TAT Improvement
15. Width Walk Control in 3D NAND Staircase Structure Etching
16. Improvement of Multi-lines bridge Defect Classification by Hierarchical Architecture in Artificial Intelligence Automatic Defect Classification
17. Impact of Asymmetric Memory Hole Profile on Silicon Selective Epitaxial Growth in 3D NAND Memory : AEPM: Advanced Equipment Processes and Materials
18. Oval-Shaped OP-Layer Hole Etching: Shape Deformation, Local Arcing, and Hole Bridging Improvements
19. Process Optimization of Contact Module in NOR Flash Using High Resolution e-Beam Inspection
20. Verification of Systematic Defects Using e-Beam Defect Review System
21. Tungsten Gate Replacement Process Optimization in 3D NAND Memory
22. Pre-Epitaxial Plasma Etch Treatment for the Selective Epitaxial Growth of Silicon in High Aspect Ratio 3D NAND Memory
23. Study of Plasma Arcing Mechanism in High Aspect Ratio Slit Trench Etching
24. A Discussion of Dielectric Film Deformation by E-Beam Energy
25. Asymmetric etching profile control during high aspect ratio Plasma etch
26. Study of Ti/TiN bump defect formation mechanism and elimination by etch process optimization
27. A 128Gb (MLC)/192Gb (TLC) single-gate vertical channel (SGVC) architecture 3D NAND using only 16 layers with robust read disturb, long-retention and excellent scaling capability
28. ANYSYS chip-level and wafer-level simulation on semiconductor process development — Yu-Chih Chang
29. Reduction of wafer arcing during high aspect ratio etching
30. Tungsten corrosion and recess improvement by feasible slurry and clean chemical in WCMP process
31. Investigation of Floating Gate Implantation Effect on 1Xnm NAND FLASH
32. Thermal Stability of Cobalt Silicide on Polysilicon Implanted with Germanium
33. Pattern dependent plasma charging effect in high aspect ratio 3D NAND architecture
34. Novel hybrid 3D NAND flash memory containing vertical-gate and gate-all-around structures
35. A case study on severe yield loss caused by wafer arcing in BEOL manufacturing
36. Wafer topology effect on the etching saturation behaviors in NF3/NH3 remote plasmas
37. The new methodology of contact process window vericification
38. Capacity simulation by cellular automation in endura platform.
39. Dishing and erosion amount prediction according pattern density calculation algorithm in 3D design layout — Kuang-Wei Chen.
40. Capacitance density and breakdown voltage improvement by optimizing the PECVD dielectric film characteristics in metal insulator metal capacitors-Chin-Tsan Yeh.
41. Advanced high accuracy scanning electron microscopy review methodology by virtual defect — Yiting Kuo.
42. Virtual metrology for 3D vertical stacking processes in semiconductor manufacturing.
43. Pattern damage and slurry behavior analysis of CMP process by mechanical and fluid simulations-Yi-Sheng Cheng.
44. Inspection sensitivity improvement by wafer sort failure sites matching algorithm — Chimin Chen.
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