Search

The short–channel behaviors of n–channel (electron–conducting) fin field–effect transistors (n–FinFETs) set at different threshold voltages were analyzed at different power supply voltages. Interesting observations were made by considering the on and off voltage states of the overdrive voltage instead of the gate–source voltage. Intrinsic transistor characteristics were revealed, enabling the comparison of short–channel characteristics between devices designed for different threshold voltages. Drain–induced barrier lowering (DIBL), subthreshold swing (SS), on/off current ratio, $\text{I}_{\mathrm{ on}}/\text{I}_{\mathrm{ off}}$ , and other parameters of the devices were considered. In addition, the novel figure of merit introduced in our previous work for the evaluation of short–channel effects, which accounts for the DIBL, SS, and $\text{I}_{\mathrm{ on}}/\text{I}_{\mathrm{ off}}$ of the devices, was also analyzed under this context. It was shown that the off–state current does not increase significantly with the increase in the supply voltage, indicating good gate control.

In this paper, we present a descriptive analysis of a performance index, ΔVDIBLSS/(Ion/Ioff), used for performance monitoring. Scaled nand p-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) (planar and FinFET devices) are included for comparison of performance trends. Also, the simplified ΔVDIBL/(Ion/Ioff) for monitoring the electrical characteristics of MOSFET devices is proposed due to the “quick measurements” required in the last step of the semiconductor manufacturing process. ΔVDIBL/(Ion/Ioff) only accounts for drain-induced barrier lowering in its numerator and on/off current ratio in its denominator. The calculation process for ΔVDIBL/(Ion/Ioff) is much quicker than for ΔVDIBLSS/(Ion/Ioff), where we need to make an extra measurement of the value of the subthreshold swing. Performance metrics, such as Ion/Ioff and intrinsic gain, gm × ro, are reported using ΔVDIBLSS/(Ion/Ioff) and ΔVDIBL/(Ion/Ioff). ΔVDIBLSS of about 100 mV in scaled MOSFETs is required to ensure that the gate control is strong. Since Ion/Ioff is a sensitive function of threshold voltage, the estimates of the ΔVDIBLSS/(Ion/Ioff) and ΔVDIBL/(Ion/Ioff) are therefore dependent on the design of threshold voltage. In planar MOSFETs, small values of ΔVDIBLSS/(Ion/Ioff) and ΔVDIBL/(Ion/Ioff) are hard to achieve. However, in FinFETs, it is easy to achieve the performance requirements due to its tri-gate structure.

This paper aims to investigate the recently proposed figure of merit, ΔVDIBLSS/(Ion/Ioff), in detail. Experimental results show that ΔVDIBLSS/(Ion/Ioff) represents the index of device immunity to short-channel effects in bulk FinFETs. The value of its numerator, ΔVDIBLSS, accounts for the drain-induced barrier lowering and subthreshold swing. The value of its denominator, Ion/Ioff, accounts for the transistor performance in transitioning between on and off states. Small ΔVDIBLSS and large Ion/Ioff are desirable, representing the improved gate control over the channel potential. We found that both ΔVDIBL and ΔVSS values are more correlated with the drain off-state current, Ioff, than they are with the drain on-state current, Ion. A high-performance FinFET device exhibits ΔVDIBLSS of about 100 mV and Ion/Ioff of about 1 × 106. Thus, ΔVDIBLSS/(Ion/Ioff) in a high-performance FinFET device is expected to be around 1×10-4 mV. Using this figure of merit, along with the verification using conventional parameters such as ΔVDIBLSS and Ion/Ioff, the proposed device shows better electrical characteristics than that in our previous work due to the optimized process conditions implemented.

This paper aims to investigate the device parameters, including drain-induced barrier lowering (DIBL), subthreshold swing (SS), and saturation drive current, Id,sat, of bulk-Si n-channel FinFET devices (bulk n-FinFETs). The impact of lightly doped drain (LDD) process on the performance of bulk n-FinFETs is also examined in this paper. According to our measured data, excluding LDD in bulk n-FinFETs not only reduces mask costs but it also enables slightly better short-channel control compared to the inclusion of LDD. A new figure of merit, ΔVDIBLSS/(Id,sat/Isd,leak), is introduced for monitoring short-channel performance of bulk n-FinFETs, where ΔVDIBLSS accounts for the DIBL and SS, and Isd,leak is the source/drain subthreshold off-state leakage current.

In this paper, we for the first time demonstrate the analog performance of a block-oxide structure in polycrystalline silicon thin-film transistor with source/drain-tie and additional poly-Si body (BO-SDT-APSB TFT) experimentally and compared with the similar device with zero block-oxide structure (SDT-APSB TFT). The block-oxide in BOSDT-SDT-APSB TFT is fabricated to reduce the drain-induced barrier lowering and channel-length modulation. The source-drain tie and additional poly-silicon body region are fabricated in both devices to improve the device performance and reduce the self-heating effect. Experimental results show that the block-oxide structure can offer enhanced gate controllability over the channel, and the transconductance (gm) of the BO-SDT-APSB TFT is therefore improved. In addition, although a higher drain conductance (gd), implying a lower output resistance r0, is observed for a BO-SDT-APSB TFT, the enhanced gm still helps to achieve the desired intrinsic voltage gain (Av = gm/gd ) behavior. [ABSTRACT FROM AUTHOR]