Search

Face Presentation Attack Detection (PAD) is critical for enhancing the security of facial recognition systems against sophisticated attacks. This study explores the use of general Image Quality Assessment (IQA) methods in face PAD, offering an alternative strategy that deviates from traditional, face-specific PAD techniques. Our evaluation of eight widely-used IQA methods across four PAD databases is structured around three distinct experimental protocols. Preliminary findings indicate that the general IQA methods are not fully effective in differentiating between genuine and attack samples, highlighting the need for modification. Nonetheless, a notable enhancement in performance is observed following the re-training of these methods using PAD datasets, bringing their effectiveness in line with that of advanced traditional PAD methods. This study provides evidence for the potential of general IQA in bolstering the resilience of face recognition systems against presentation attacks.

This study demonstrates the first work that achieves accurate modeling of Hydrogen plasmatreated (H-treated) p-GaN gate devices with the ASM-GaN model, facilitating simulations for applications in monolithic integrated circuit (IC) design. The workflow for ASM-GaN model parameter extraction and optimization using IC-CAP is proposed. The I-V characteristics of both Enhancement / Depletion (E/D) mode devices are modeled and fitted. The impact of device capacitance on the dynamic properties of monolithic IC is investigated through the ASM model. The results demonstrate that Cds, Cgd, and Cgs have different effects on the monolithic logic circuit performances. The high-level fitting of experimental data and circuit simulation of Inverter, NAND, and Comparator circuits proves the credibility of the modeling workflow and device capacitance modulation. This work provides a method to speed up the GaN monolithic IC design by accurate modeling with fast parameter extraction workflow regardless of the fabrication process. The reliable prediction of the circuit’s dynamic performance will lay the foundation for designing and scaling up the GaN monolithic IC application.

In intersatellite laser communications, the centroiding accuracy of a laser spot is crucial for maintaining steady communication links. However, the systematic error introduced by discrete sampling restricts further improvement of centroiding accuracy when choosing algorithms that are widely used in engineering. Additionally, the ultrahigh computational complexity and multiple-step iterations of the Gaussian fitting (GF) algorithm are unsuitable for real-time implementation, even though the algorithm can achieve the highest centroiding accuracy. In this study, we propose a laser spot centroiding algorithm based on template correlation to simultaneously satisfy the requirements of real-time performance and accuracy. The proposed algorithm evaluates the central location of a laser spot by obtaining the index of the maximum Pearson correlation coefficient (PCC). Simulations performed under different conditions reveal that the proposed algorithm is robust against the interference of background noise and the bad pixels. Moreover, experimental verification is performed based on the implementation on a Field-Programmable Gate Array (FPGA) in real-time, meanwhile its accuracy is on the same level as that of the GF algorithm and better than those of other widely-used algorithms. Therefore, the proposed algorithm is suitable for accurate real-time locating of laser spots in engineering applications of the intersatellite laser communications.

The fingerprint positioning has achieved remarkable results in indoor localization tasks, but the method usually relies on a large amount of fingerprint data to build a fingerprint database, and the amount and diversity of fingerprint data will directly affect the effectiveness of fingerprint positioning. Since fingerprint acquisition is limited and disturbed by space and time, it consumes a lot of labor and time costs to collect fingerprint data in the localization environment, and wireless fingerprint data is time-sensitive and environment-dependent, and changes in the localization environment will reduce the usability of the existing fingerprint database. The complex and repetitive fingerprint acquisition work seriously affects the feasibility of practical deployment of fingerprint positioning systems in the positioning environment. Therefore, the study of low-cost wireless fingerprint database construction methods has become an inevitable part of promoting the widespread deployment of indoor fingerprint positioning systems. In this paper, we introduce the traditional data augmentation-based approach and the advanced machine learning model-based approach, systematically presenting the underlying models and algorithms of both. The former reviews the application of two traditional data enhancement methods, namely channel propagation models and interpolation or regression, to the construction of low-cost wireless fingerprint databases, while the latter taps into techniques for reducing the cost of fingerprint database construction by combining generative adversarial networks and small-sample learning models with the indoor localization domain. Finally, we discuss the current challenges and future research directions for achieving high-performance indoor localization based on low-cost wireless fingerprint databases, and suggest some useful research guidelines.

In this work, dual-gate enhancement-mode (E-mode) device based NAND circuit (DG-NAND) and the NAND block with double E-mode devices (DD-NAND) are developed and fabricated based on the GaN MIS-HEMTs (metal-insulator-semiconductor-high-electron-mobility-transistors) platform. The DG-NAND circuit has an area of 0.118 mm2 with the probe pad, which is 24% lower than the area of the DD-NAND circuit. Both static and dynamic experimental results validate the advantages of performance improvement of NAND circuits designed by dual-gate technology at an input voltage of 9 V. This paper demonstrates the design potential of dual-gate NAND in an all-GaN MIS-HEMTs platform through compact design.

SiC MOSFETs devices with double-trench dominate the market due to their low on-resistance. However, studies on its temperature-dependent properties are not comprehensive. This work uses fast I-V and static I-V techniques to explore the location of electrons trapped in the device under moderate gate stress. Threshold voltage instability ( ${\mathrm {V}}_{\mathrm {TH}}$ hysteresis and $\Delta{\mathrm {V}}_{\mathrm {TH}}$ ) and on-resistance degradation ( $\Delta{\mathrm {R}}_{\mathrm {ON}}$ ) are used to characterize oxide trapping. Although the observation method is different, it can be found that the ${\mathrm {V}}_{\mathrm {TH}}$ instability and ${\mathrm {R}}_{\mathrm {ON}}$ degradation increase linearly with logarithmic time over a wide time range from $100~\mu{\mathrm {s}}$ to 104 s, suggesting that the direct tunneling mechanism dominates the electrons trapping in the oxide near the SiO2/SiC interface. The interface trap density is $3.8\times 10^{12}$ cm−2 $\cdot$ eV−1. In addition, a negative temperature dependence is shown in the test, and the fitting parameter $\gamma$ from 0.16 to 0.18 indicated that these traps are concentrated in the oxide layer. These traps’ energy level at 0.68 eV below the conduction band was obtained in the recovery phase through the Arrhenius plot.