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The morphology algorithms are an exciting field that provides a powerful and unified method applied to image and video processing applications. Also, they have many advantages to give manageable hardware implementations and are widely employed as parts of image processing techniques. On the other hand, Quantum-dot Cellular Automata (QCA) is a promising and novel nanotechnology that contains notable benefits against common technologies in diverse features like extremely small size, low energy loss, and high operation frequency. Besides, schematizing circuits with no info loss or fault-tolerant might be beneficial in reducing power wastage. In the present paper, we suggest a novel fault-tolerant procedure to execute the morphology operations in digital image processing based on QCA. The mentioned fault-tolerant schematization for executing the morphology operations in digital image processing is easy to build. It contains notably lower elements than Complementary Metal Oxide Semiconductor (CMOS) design. Implementation and testing of all circuits are achieved using the QCADesigner tool. The suggested fault-tolerant circuit for morphological dilation/erosion operation attains high fault-tolerant in all cases of defects. [ABSTRACT FROM AUTHOR]

Some of the vital problems around the conventional CMOS technology are leakage-power consumption, physical-scalability limits, and short-channel effects. These deficiencies have led to many studies about nano-scale designs. Quantum dot cellular automata (QCA) is a potential answer in nanotechnology. Scholars have considered the four-dot squared cell as the main factor in the QCA. Also, a full-adder is a fundamental unit in every digital system. However, the importance of cell and area consumption limitation in circuit designing has been completely ignored in most of the related studies. Therefore, in this paper, we have offered a one-bit multi-layer full-adder cell. The practical accuracy of the proposed circuits has been assessed using QCADesigner. According to the obtained results and the design, the presented design has efficient cell usage against all the prior designs regarding cell counts and area occupation, leading to around 7% improvement in cell number than the common full-adder design. The simulation outcomes have also shown that the introduced design has excellent efficiency regarding cell and area aspects. [ABSTRACT FROM AUTHOR]