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The constant growth of social media, unconventional web technologies, mobile applications, and Internet of Things (IoT) devices create challenges for cloud data systems in order to support huge datasets and very high request rates. NoSQL databases, such as Cassandra and HBase, and relational SQL databases with replication, such as Citus/PostgreSQL, have been used to increase horizontal scalability and high availability of data store systems. In this paper, we evaluated three distributed databases on a low-power low-cost cluster of commodity Single-Board Computers (SBC): relational Citus/PostgreSQL and NoSQL databases Cassandra and HBase. The cluster has 15 Raspberry Pi 3 nodes with Docker Swarm orchestration tool for service deployment and ingress load balancing over SBCs. We believe that a low-cost SBC cluster can support cloud serving goals such as scale-out, elasticity, and high availability. Experimental results clearly demonstrated that there is a trade-off between performance and replication, which provides availability and partition tolerance. Besides, both properties are essential in the context of distributed systems with low-power boards. Cassandra attained better results with its consistency levels specified by the client. Both Citus and HBase enable consistency but it penalizes performance as the number of replicas increases. [ABSTRACT FROM AUTHOR]

An artificial intelligence of things (AIoT) chip is a critical hardware component in edge devices that supports data acquisition and processing in the artificial intelligence (AI) era. In this paper, we introduce the architecture and circuit techniques for AIoT systems as well as the design challenges associated with them. To address the design challenges, we describe our design approaches to improve energy efficiency from the standpoints of system architecture, AI computing, and data acquisition circuits. Meanwhile, we present our most recent research progress and state-of-the-art AIoT chip demonstrations at a prestigious conference. Our design techniques improve power and energy efficiency by orders of magnitude on corresponding state of the arts (SOTA), allowing for an advanced AIoT chip design. [ABSTRACT FROM AUTHOR]

Wireless Body Area Network (WBAN) is a wireless network of short-range communication protocols for remote healthcare monitoring with the possibility of giving freedom of human body movements. Sensor nodes (motes) are usually located under the skin, implanted deep in the body, or ingested, as in the rare case of smart pills for medical and non-medical usage. Since the necessary connections of wearable and implantable devices are wireless, and the components use low batteries, processing and transferring the critical data can deplete the nodes' power. In most cases, it is impossible to exchange or re-power batteries. Holter monitoring, loop recorders, and wireless capsule endoscopy are some of the WBAN's applications for saving and transferring medical data. Wireless capsule endoscopy is the application for image transmission in WBANs, and the image compression in common is a specific segment of capsule endoscopy. Since the better compression of images increases the frame rate and typically improves the diagnosis process, selecting the compression algorithm should be relevant. The considerable scope of this comprehensive study pays attention to the various biomedical data compression approaches in WBANs. This paper focuses on power-efficient schemes of remote healthcare networks. In this survey article, the energy-based biomedical data compression approaches of WBANs and remote healthcare networks are accurately classified based on lossy, lossless, and hybrid techniques; later, a comprehensive comparison of each specific method's power consumption is presented. [ABSTRACT FROM AUTHOR]

This paper proposes a modified Schmitt-trigger (ST)-based single-ended 11 T (MST11T) SRAM cell. The proposed cell is best suited to ultra-low voltage applications. Two ST-based cross-coupled inverters comprise the storage cell of the proposed MST11T bit cell. In comparison with conventional inverters, ST-based inverters have sharp voltage transfer characteristics. As a result, the proposed bit cell's stability performance increases. The proposed SRAM cell's leakage power consumption is reduced because of the use of stacked N-type transistors. For the read operation of the proposed bit cell, the read decoupled technique is used. As a result, the read static noise margin (RSNM) has greatly improved. The proposed bit cell's write static noise margin (WSNM) is increased by adopting feedback-cutting methodology. The performance of the proposed bit cell is compared with that of conventional 6 T, conventional 8 T, Schmitt-trigger 10 T (known as ST2), modified PMOS-PMOS-NMOS-based cell core 10 T (MPPN10T), feedback-cutting 11 T (FC11T), Schmitt-trigger 11 T (ST11), and Schmitt-trigger 12 T (ST12T) cells. According to the simulation results, the proposed MST11T SRAM cell has RSNM of 2.42, 1.18, 1.71, 1.30, and 1.80 times higher when compared to 6 T, FC11T, ST2, MPPN10T, and ST12T, respectively. The WSNM of the proposed bit cell has been increased by 1.56, 2.44, 1.28, 1.71, 1.35, 1.52, and 1.02 times, respectively, over 6 T, 8 T, ST2, MPPN10T, FC11T, ST11T, and ST12T. Furthermore, the suggested cell has a read delay that is 1.32, 1.79, and 1.53 times lower than ST11T, FC11T, and ST12T, respectively. The proposed bit cell has a write delay that is 1.14 and 1.63 times lower than FC11T and ST11T, respectively. The proposed MST11T bit-cell consumes 3.74, 1.56, 4.59, 5.38, and 4.83 times less leakage power than the 8 T, ST2, MPPN10T, FC11T, and ST12 bit-cells, respectively. When compared to 8 T/ST2/MPPN10T/ST12T at 0.2 V supply voltage, the enhanced facts incur a 4.87/3.79/3.78/1.97 penalty in write delay. The figure of merit (FOM) is derived as a result of this extensive access to the revolutionary SRAM cell performance, i.e., offering greater values at a 0.2 V DC supply voltage. In addition, the paper examines the impact of manufacturing process and temperature changes on MST11T cell enactment, as well as the circuit robustness using HSPICE with 7-nm FinFET technology. [ABSTRACT FROM AUTHOR]

This paper presents static and dynamic theoretical analysis of a new Operational Transconductance Amplifier (OTA) dedicated to low-voltage and low-power applications. High linearity is obtained using signal attenuation for rail-to-rail operation. Design, layout and post-layout simulations have been carried-out with Cadence Virtuoso in a 0.18µm CMOS technology. Post-Layout Simulation (PLS) demonstrates proper operation down to ± 0.75 V supply voltage with a high open loop small-signal voltage gain of 58.26dB, a unity gain frequency of 18MHz and a total harmonic distortion of -66.55dB at 100 kHz for a peak-to-peak input voltage of 0.8V. Based on this circuit, two applications have been successfully demonstrated: on the one side, a 5th order Butterworth G mC filter and, on the other side, a voltage mode instrumentation amplifier. [ABSTRACT FROM AUTHOR]

Portable applications and battery-operated devices require highly reliable, stable, and low-power nanometer-sized embedded cache static random access memory (SRAM) cells. The conventional 6-transistor (6 T) SRAM cell and its variants suffer from malfunctioning during the read/write operations, and instability, and are vulnerable to the multi-bit soft-error rate at scaled technology node and low supply voltage (VDD). In this regard, this paper proposes an 12 T SRAM cell with reliable functioning and reduced multi-bit soft-errors appropriate for low-power portable applications. This cell performs single-end bitline decoupled read operation and write data-dependent feedback-cutting-aware differential write operation to improve the read static noise margin (RSNM) and write static noise margin (WSNM), respectively. The presence of stack transistors in the cell core and read path, and also high virtual ground (VGND) minimize the leakage power dissipation. The proposed cell is compared with other state-of-the-art SRAM cells at VDD = 0.7 V and under harsh process, voltage, and temperature (PVT) variations. It offers at least 1.18X higher RSNM, 1.27X higher WSNM, and 2.02X lower leakage power dissipation. It also shows the second-best read power and incurs a penalty in write power. This cell shows at least 1.17X, 1.32X, and 1.04X smaller spread in read delay, RSNM, and WSNM, respectively, when subjected to PVT variations. In addition, the proposed cell eliminates the write half-select disturbance by employing a separate gate to drive the access transistors and thus column-interleaving structure and error correction coding can be applied to reduce multiple-bit upset and increase soft-error immunity. The soft-error in the proposed cell is reduced by at least 1.37X in critical charge. Generally, the proposed cell offers the best overall performance among all the compared cells by showing the highest proposed figure of merit. [ABSTRACT FROM AUTHOR]

Variable energy constraints affect the implementations of neural networks on battery-operated embedded systems. This paper describes a learning algorithm for randomization-based neural networks with hard-limit activation functions. The approach adopts a novel cost function that balances accuracy and network complexity during training. From an energy-specific perspective, the new learning strategy allows to adjust, dynamically and in real time, the number of operations during the network's forward phase. The proposed learning scheme leads to efficient predictors supported by digital architectures. The resulting digital architecture can switch to approximate computing at run time, in compliance with the available energy budget. Experiments on 10 real-world prediction testbeds confirmed the effectiveness of the learning scheme. Additional tests on limited-resource devices supported the implementation efficiency of the overall design approach. [ABSTRACT FROM AUTHOR]

This paper presents a sub-microwatt sub-bandgap voltage and current reference that can generate proportional-to-absolute-temperature (PTAT) and complementary-to-absolute-temperature (CTAT) currents concurrently. The voltage reference is derived from the process-insensitive silicon bandgap voltage of a bipolar junction transistor, whereas the current reference is made by combining PTAT and CTAT currents. Line regulation is improved by incorporating cascode devices without an operational amplifier (opamp). Fabricated in a standard 0.18-µm CMOS process, the proposed bandgap reference occupies an active area of 0.4 mm2. The current and voltage reference ( I REF and V REF ) are measured as 170 mV and 21 nA, respectively, while the start-up settling response is measured as 20 ms at room temperature. The average temperature coefficient of I REF and V REF is 79.8 ppm/°C and 87.93 ppm/°C across the temperature range from − 40 to 120 °C, respectively. The power consumption is 134 nW at the minimum supply voltage of 1.2 V. The power supply ripple rejection of V REF is measured as − 10 dB at 100 kHz without any filtering capacitor, when the 1.6 V input line voltage is distorted by a 300-mVp-p ripple. The measured line sensitivity of the voltage and current reference is 0.142%/V and 0.757%/V, respectively. [ABSTRACT FROM AUTHOR]

IoT and wearable medical devices frequently require ultra-low power solutions that can support long spells of inactivity. This study presents a buck converter to control power stages using a novel pulse frequency modulation (PFM) system that reduces switching losses for low-power systems. The modulation of high and low-frequencies was demonstrated, where the high-frequencies exhibited better energy transformation between the inductor and capacitor, and the low-frequencies could be adjusted for different current loads, to reduce switching losses. This circuit is optimized for light load applications. Using voltage control oscillation (VCO), the frequency range of 0.5 MHz – 2.0 MHz can be adjusted to influence conversion efficiency for different loads. The design was simulated and then fabricated using TSMC 0.18um process. The core size was about 1500 × 1000um that includes power MOS. Measurements result an average conversion efficiency of 91% under a load of 0.1 mA – 10 mA. This chip is suitable for battery-based IoT systems, or wearable medical devices. [ABSTRACT FROM AUTHOR]

This paper proposes a new discrete cosine transform (DCT) processor. The micro-rotation section of the architecture is based on a shared-resource improved coordinate rotation digital computer (CORDIC) unit, in an enhanced scalable DCT engine. To reduce the resources, and utilization area all micro-rotation operations have implemented as one united block in overlapped form. Using one processing element, the memory-based architecture has reduced the power consumption. Inputs and outputs of the processor are in-order which can be taken into account as an advantage for the proposed design. The processor has a low-complexity and distributed controller. Furthermore, due to the shared-resource implementation of CORDIC-II unit, by reduction of adding, shifting operations both in size, and number, the processor has high capabilities in short word lengths in comparison with state-of-the-art DCT processors. Compared to existing prominent DCT processors, the proposed processor achieves better results with limited hardware resources. [ABSTRACT FROM AUTHOR]

Static random-access memories (SRAMs), which are the most ubiquitous in modern system-on-chips, suffer from high power dissipation and poor stability in advanced complementary metal–oxide–semiconductor (CMOS) technology due to continuous learning, which leads to increased short-channel effects (SCEs), thereby, leading to use of new nano-devices. The fin-shaped field-effect transistor (FinFET) with lots of impressive attributes like mitigated SCEs is an efficient replacement for CMOS to overcome the aforementioned concerns. In this regard, this paper aims to explore a novel single-bitline 9-transistor (SB9T) SRAM with bit-interleaving capability appropriate for low-power near-threshold operation in 7-nm FinFET technology. The relative performance of the proposed SB9T is estimated by comparing it with other seven contemporary SRAMs such as conventional 6 T, write–read enhanced 8T (WRE8T), transmission gate read decoupled 9T (TGRD9T), one-sided Schmitt-trigger 9T (ST9T), data-independent read port 10T (DIRP10T), PMOS-PMOS-NMOS-based cell core 10T (PPN10T), and feedback-cutting 11 T (FC11T) at a near-threshold supply voltage of 0.5 V. Simulation results inferred that the SB9T offers 1.77 × /1.36 × and 2.35 × /13.13 × /1.30 × improvement in read stability and writability compared to WRE8T/ST9T and 6 T/DIRP10T/PPN10T, respectively. Furthermore, it consumes the best dynamic read power, which is at least 1.50 × , the third-best dynamic write power, and the second-best static power. The proposed SB9T SRAM offers 2.89 × /2.37 × improvement in dynamic write power/static power, at the expense of 1.742 × area overhead, compared to 6 T. [ABSTRACT FROM AUTHOR]

This paper investigates a novel highly stable and robust single-ended 10T SRAM cell appropriate for low-power portable applications. The cell core of the proposed design is a combination of a normal inverter with a stacked NMOS transistor and a Schmitt-trigger (ST) inverter with a double-length pull-up transistor. This improves hold stability and leakage power dissipation. The read and write operations of the proposed cell are performed with the aid of separated paths and bitlines, lowering power consumption. The strong cell core and decoupled read path eliminate the read-disturbance issue in the proposed cell, resulting in read static noise margin (RSNM) enhancement. Furthermore, the feedback-cutting write-assist technique used in the proposed design mitigates the writing '1' issue; consequently, write static noise margin (WSNM)/write margin (WM) improves. To prove the superiority of the proposed SRAM cell in various performance metrics, it is compared with state-of-the-art SRAM cells, introduced as 6T, TG9T, 10T-P1, and SB11T, using HSPICE and 16-nm CMOS technology node taking into consideration the impact of the severe process, voltage, and temperature (PVT) variations. Obtained results at VDD = 0.7 V show that the proposed design offers the highest HSNM/RSNM/WSNM (or WM). The read/write delay of the proposed cell is 3.92X/2.37X higher than that of the 6T SRAM cell due to its single-ended reading/writing structure. However, in terms of power consumption, the proposed cell exhibits 1.64X/1.54X lower than that of 6T SRAM cell. Though the proposed cell occupies a 1.24X higher area compared with the 6T SRAM cell due to its higher count of transistor, it shows the highest proposed figure of merit among all the studied SRAM cells, which is 26.90X higher than that of 6T SRAM cell. [ABSTRACT FROM AUTHOR]

In this paper, the impact of the inductive peaking bandwidth enhancement technique on the input-referred noise performance of a 10 Gbps optical receiver, which includes the CMOS Regulated Cascode (RGC) Transimpedance Amplifier (TIA) is investigated and analyzed. By examining the noise equations in this paper, a novel low-noise design methodology, is introduced. Additionally, through the implementation of the structured gm/ID\documentclass[12pt]{minimal}\usepackage{amsmath}\usepackage{wasysym}\usepackage{amsfonts}\usepackage{amssymb}\usepackage{amsbsy}\usepackage{mathrsfs}\usepackage{upgreek}\setlength{\oddsidemargin}{-69pt}\begin{document}$${\text{g}}_{\text{m}}/{\text{I}}_{\text{D}}$$\end{document} approach and by selecting the suitable transistor dimensions, the power consumption as well as the noise values are reduced, while the values of the obtained gain and bandwidth are increased. To verify the performance of the designed TIA, the circuit issimulated in HSPICE using 90 nm CMOS technology parameters. The simulation results show the obtained gain value of 55.45 dBΩ, a bandwidth of 7.51 GHz and an input referenced noise value of 15.7 pA/√Hz at the 1.2 V power supply, while the circuit consumes 0.75 mW of power. [ABSTRACT FROM AUTHOR]

In this paper, a new high-gain operational transconductance amplifier (OTA) circuit is designed. The proposed circuit uses bulk-driven technique to reduce the required supply voltage while gain-boosting as well as positive feedback techniques are used to increase the gain of the circuit and compensate the gain reduction effect due to the use of bulk-driven transistors. The performance of the proposed circuit is simulated using 180-nm CMOS technology parameters and is optimized using an optimization algorithm for the main purpose of minimizing the power consumption of the circuit. Simulated performance of the proposed circuit for 1.2 V DC supply voltage shows 94.8 dB gain, 203-MHz bandwidth, and slew-rate of 365-V/µS while occupying die area of 1360 µm2. However, the proposed circuit is also designed for a low-voltage scenario with 0.75 V DC supply voltage that results in 73.7 dB gain, 131-MHz bandwidth, and slew-rate of 149-V/µS. [ABSTRACT FROM AUTHOR]

This paper presents the design and analysis of a new low-voltage and low-power OTA-C universal filter which can realise four different system topologies including: Single-Input Single-Output (SISO), Single-Input Multi-Output (SIMO), Multi-Input Single-Output (MISO) and Multi-Input Multi-Output (MIMO), without any requirement of extra switching or adding other active elements to the core filter circuit. In addition, the proposed circuit has the ability to operate in all modes of operation (multi-mode) using the grounded capacitors to effectively reduce the parasitic effects. Furthermore, to decrease the power consumption effectively, the proposed OTA-C filter is biased in the subthreshold region which significantly reduces the power consumption. Moreover, the proposed circuit has a very low sensitivity to the values of transconductance and capacitance elements. Finally, the performance of the proposed universal filter is simulated in HSPICE, using 0.18 µm CMOS technology parameters. However, the simulation results justify the design accuracy and low-power performance as well as the capability of generating filtering responses simultaneously in the different system configurations. [ABSTRACT FROM AUTHOR]

This research proposes a novel scalable Discrete Cosine transform (DCT) processor. It is based on a shared-resource enhanced Coordinate Rotation Digital Computer (CORDIC) unit, in a modified Loeffler architecture. All micro-rotation operations have moved to the last stages, and are implemented as one unified block in an overlapped form to reduce the utilization area. Also, the beginning stages consist of multiple-delay feedback butterfly units. The hardware-efficient pipelining method of the processor is another reason to reduce the power consumption. This is important while the purpose is resource-constraint IoT devices whereas establishing strong edge servers is not feasible everywhere. Especially in the case of modern video compression standards which demand higher points for DCT such as high efficiency video coding (HEVC) low-power design is crucial. Ubiquitous computing, Big Data and Cloud Services, IoT-Enabled Web are computation-intensive applications. Thus, power reduction of wireless networks of sensors such as, Bluetooth, RFID Wi-Fi, and smartphones, tablets, camcorders are in great demand. In-order input, and output is the proposed design’s advantage. Furthermore, due to utilization of shared-resource CORDIC-II unit, and reduction of adding, shifting operations, in size, and number, the architecture has high performance in short word lengths (WL) in comparison to state-of-the-art DCT processors. [ABSTRACT FROM AUTHOR]

A new current-mode fractional-power CMOS circuit such as cube-root and squared-cube-root configurations that give output signal in four quadrants has been presented for the first time. MOSFETs utilized in the design exploit translinear principle in weak-inversion region. The second-order effects on the circuit proposition have been analysed. The implementation justification has been validated by post-layout simulation on Virtuoso-SPECTRE tool with 180 nm GPDK CMOS process parameters. It has been found that using ± 0.5 V supply voltage, the realized cube-root and squared-cube-root circuits work for an input range of ± 30 µA while consuming few hundred nano-watts of static power and exhibit a maximum of ± 1 dB error over a wide input range of ± 1.5 µA to ± 30 µA in all four quadrants. Utility of the proposed circuits, as companding and gamma corrector, has also been elaborated. [ABSTRACT FROM AUTHOR]

A new 1-bit digital comparator named 14T-SR-GDI is presented with gate-diffusion-input (GDI) and single-swing-restoration (SR) techniques to attain internal gates with high driving capability. The comparator has 14 transistors which produce full-swing outputs with low power consumption. In the 14T-SR-GDI, boosted inner signals are used to activate the output gates which result in a high-speed circuit with effective scalability and the enhanced driving capability for multi-bit structures. The comparator has a low power delay product (PDP) due to the small numbers of internal nodes and capacitances and efficient power-ground-free gates. The 14T-SR-GDI comparator, fully SR-GDI-based AND, and OR gates, construct a new tree structure for multi-bit magnitude comparators including 2-bit, 4-bit, 8-bit, and 16-bit comparators. The proposed 1-bit comparator is used in image processing for difference detection, and its efficiency is proved by image quality parameters. The post-layout simulations are performed for the 1-bit to 16-bit structures under TSMC 90 nm technology. The extracted results express a PDP with an average difference of 9.59% between the regular and post-layout modes. Also, the proposed 16-bit comparator is embedded in a pad with a total area of 4331.25 μm2. The designed magnitude comparators are key components in digital signal processors (DSPs). [ABSTRACT FROM AUTHOR]

The smart temperature sensor measures the room temperature and converts it to the digital domain, thus making it easier to process and store data. This work presents a fully integrated smart temperature sensor implemented in a 180 nm CMOS technology suitable for low voltage and ultra-low power electronic applications. The designed circuit uses a frequency to digital conversion topology, in which the frequency of an internal signal is linearly dependent on the room temperature. The minimum supply voltage for the designed circuit is only 0.5 V, while the occupied silicon area is 0.04 mm2. By employing a simple frequency doubler circuit and proper circuit topologies, a very low power consumption of 19 nW for a sampling frequency of 100 Hz at 27 °C is achieved. Moreover, the sensor consumes nominally 190 pJ per conversion. The simulated inaccuracy using nominal (TT) transistor models is lower than 0.5 °C over a wide temperature range of − 30 °C to 100 °C. Preliminary silicon data shows the functionality of the design circuit. Additionally, the effects of the external clock signal temperature coefficient on the performance of the designed circuit were discussed, and a correction method was proposed. [ABSTRACT FROM AUTHOR]

In this work, we propose a rail-to-rail output buffer with low static-power and high speed for OLED display applications. To guarantee low static power consumption, low tail-current is designed in the buffer's first stage and the output stage is cut off in the static operation. To improve the transient response, dynamic-current-bias technique is used, and it also improves the system stability by pushing away the non-dominant pole. Meanwhile, we balance the large-signal slew-rate and system stability with dual-output buffer structure. Placing compensation resistor across the dual outputs creates zero for suitable phase margin, while the real output still behaves with low ON resistance and keeps high slew rate. The proposed design has been verified by a 0.18 μm 1.8 V/5 V CMOS process, which shows that the buffer only draws 2.8-μA static current. Under a 1-nF capacitance load and a 5-V power supply, the buffer achieves 1.18-μs settling time, which is only 41% of the single-output-stage structure with the same chip size (52 μm × 59 μm). [ABSTRACT FROM AUTHOR]

This work presents the design of a low voltage dynamic comparator for low-power ADC applications. The dynamic comparator uses a pre-amplifier powered by a floating reservoir capacitor and a positive feedback bulk structure. The output stage comprises a simple circuit to reduce the total voltage overhead necessary to define the logic levels. The powering scheme of the pre-amplifier, with a floating reservoir capacitor, contributes to reduce the impacts of global process variability. The positive feedback bulk structure lowers the threshold voltages of the pre-amplifier transistors at the sampling phase. Such structure also provides positive feedback signal during the comparison phase to provide extra transconductance. The proposed dynamic comparator is designed and simulated in a 28 nm CMOS technology and reaches an IRN below of the quantization noise of a 10 bits differential ADCs working with 600 mV power supply. The dynamic comparator achieves 237 μV input-referred noise, while consuming only 38.8 fJ per comparison and having a nominal delay of 5.77 ns. [ABSTRACT FROM AUTHOR]