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Soft errors are the primary concern in space and terrestrial integrated circuit applications. When a charged particle from space collides with a scaled memory circuit, a transient pulse is generated across the sensitive storage node, causing a bit flip throughout the storage nodes. This bit flip is stated as a soft error, which affects the semiconductor memory architecture's stability and reliability. This paper presents a 10 T SRAM (STS-10 T) cell that mitigates soft error challenges even at space temperature. To demonstrate the relative performance of the STS-10 T, existing radiation-hardened memory cells, such as the Quatro-10 T, PS10T, NS-10 T, RHBD-10 T, 10 T-SRAM, RHMD-10 T, QUCCE-10 T, and SIS-10 T, were evaluated. The read stability of the proposed STS-10 T memory cell is 2.6x/ 3x/ 1.5x/ 1.4x/ 1.25x/ 1.6x/ 2.03 × greater than that of the existing Quatro-10 T/ NS-10 T/ PS-10 T/ RHBD-10 T/ RHMD-10 T/ QUCCE-10 T/ SIS-10 T memory cells, respectively. Moreover, 1.48x/ 1.17x/ 1.18x/ 1.4x/ 1.01x/ 1.27x/ 1.45x/ 1.43 × greater write ability than Quatro-10 T/ NS-10 T/ PS-10 T/ RHBD-10 T/ 10 T-SRAM/ RHMD-10 T/ QUCCE-10 T/ SIS10T. In addition, when the supply voltage is at 1 V, the read and write access time, hold power, and critical charge is also improved. [ABSTRACT FROM AUTHOR]