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The isolated current‐fed push‐pull dc‐dc converter has some practical advantages such as improved cross regulation characteristics, reduced output noise, and good overall efficiency. Although detailed insight on this converter is available in the literature, the use of digital peak current mode with slope compensation control methodology has not been explicitly presented. This paper discusses digital peak current mode control of a current‐fed push‐pull converter with a novel double digital pulse‐by‐pulse current limiting scheme. Push‐pull topology is implemented on the primary side of an isolation transformer in a dc‐dc bidirectional converter. Achieving this control solution of isolated push‐pull converter is attractive especially in controlling battery power flow in smart micro‐grids. By using a digitally controlled push‐pull converter, the ability to change controller parameters and the use of droop control methods for storage are easier. Furthermore, current mode control provides capability of equal current sharing between parallel converters and eliminates the transformer saturation problem that is common in push‐pull topology. Using continuous time model of the converter, a Type II compensator is designed and implemented in discrete time domain. Digital slope compensation is applied to eliminate the high frequency oscillations caused by current feedback loop. The control method and slope compensation are implemented on STM32F303 mixed‐signal microcontroller. On‐chip analog comparator disabled the PWM output if the sensed current exceeds the reference current until next PWM cycle. The digital controller performance is confirmed by 13 W hardware implementation including fast transient response and stable operation. [ABSTRACT FROM AUTHOR]

This paper presents an energy‐efficient digital‐to‐analog converter (DAC) switching method with low common‐mode variations for high‐resolution successive approximation register (SAR) analog‐to‐digital converters (ADCs), while enabling to implement resolutions such as 14‐bit as compared to the typical 10‐bit. The proposed switching method enables high resolution by having a nearly constant common‐mode voltage and employing input‐swapping to use the reference voltage (Vref) only in the sampling phase. This method eliminates the need for the third reference voltage during the entire DAC switching steps, which reduces the required number of switches at the bottom plates of the capacitors. The use of lower number of switches not only lowers the DAC control logic complexity, but also results in a faster operation, lower power, and smaller area. When compared to conventional 10‐bit SAR ADCs, the proposed switching method in a 10‐bit implementation reduces the average energy and area by 96.09% and 75%, respectively, while offering high‐resolution implementation options such as 14 bits. [ABSTRACT FROM AUTHOR]

In this paper, digital parallelization and fractional delay‐based novel methods are proposed for the realization of high bandwidth, high‐resolution Ku‐band radar target simulator with 2.5 GHz intermediate frequency. High bandwidth waveform from radar is sampled by high‐speed Analog to Digital Converter, and samples are parallelized in Field Programmable Gate Array (FPGA) to work at the nominal clock frequency. In Digital RF Memory‐based target simulator, for finer range resolution, the FPGA clock frequency needs to be increased, which leads to increased system design complexity. The finer range resolution is accomplished without altering the system clock frequency using variable fractional delay filters and the digital parallelization methodology is proposed in this paper. The maximum target range that can be simulated is 20 km. As a result, memory requirements, computational complexity, and power dissipation are reduced. Finally, simulation and implementation results are presented. [ABSTRACT FROM AUTHOR]

This paper proposes a background calibration scheme for the pipelined‐Successive Approximation Register (SAR) Analog‐to‐Digital Converter (ADC) based on the neural network. Due to the non‐linear function fitting capability of the neural network, the linearity of the ADC is improved effectively. However, the hardware complexity of the neural network limits its application and promotion in ADC calibration. Hence, this paper also presents the optimization schemes, including the neuron‐based sharing neural network and the partially binarized with fixed neural network, in terms of calibration architecture and algorithm. A 60 MS/s 14‐bit pipelined‐SAR ADC prototyped in 28‐nm technology is utilized to verify the feasibility of the proposed calibration method. The measurement results show that the proposed calibration greatly enhances the Spurious Free Dynamic Range (SFDR) and Signal‐to‐Noise‐and‐Distortion Ratio (SNDR) from low frequency to Nyquist frequency. Meanwhile, the original calibrator and improved calibrator are synthesized in Synopsys Design Compiler to compare their hardware complexity. Compared with the unoptimized version, the optimized schemes can decrease the logic area and the network weights up to 76% and 52%, with negligible loss in calibration performance. [ABSTRACT FROM AUTHOR]

This paper presents a novel dynamic bias latch‐type comparator combined with a voltage‐controlled delay line (VCDL), designed specifically for low‐power and low‐noise applications in high‐speed analog‐to‐digital converters (ADCs). The incorporation of the VCDL precedes the dynamic bias amplifier in the proposed comparator, thereby achieving a balance between energy efficiency and high‐speed operation. This innovative design enhances the input common voltage of the dynamic bias amplifier through the utilization of the VCDL, surpassing that of a conventional dynamic bias comparator. Furthermore, it demonstrates increased adaptability in technology scaling and efficient operation at lower supply voltages, leveraging inverters and other simple cells. The proposed comparator in 28 nm process technology achieves a 309.7 µV input‐referred noise while consuming approximately 145.8 fJ and completing comparisons in 125 ps with a 0.9 V supply and a 0.45 V input common‐mode voltage. [ABSTRACT FROM AUTHOR]

Summary: This paper presents an energy‐efficient fully differential switching scheme for successive approximation register (SAR) analog‐to‐digital converters (ADCs). During the sampling phase, the top and bottom plates of all capacitors except most significant bit (MSB) capacitors are grounded in digital‐to‐analog converter (DAC) arrays. The input signals are bottom plate sampled on MSB capacitors. This technique can reduce the settling time by more than 87.5% in comparison with the conventional switching scheme. Furthermore, a novel reset‐free regenerative comparator is unveiled in this paper. The proposed comparator is armed to amplify its inputs both during the reset and evaluation phases. In comparison with a conventional single‐ended comparator, the proposed comparator can reduce power consumption above 90% for the almost same input‐referred offset voltage. The proposed scheme is designed with a resolution of 8‐bit and a sampling rate of 90 MS/s in a standard 65‐nm CMOS technology. The simulation results certify that the ADC dissipates 363‐μW power with a 1.2‐V supply voltage and achieves a 7.13 effective number of bits (ENOBs), yielding a 28.8 fJ/conversion step Nyquist rate Walden FOM. [ABSTRACT FROM AUTHOR]

The time‐interleaved analog‐to‐digital converter (TIADC) system could achieve high sampling rate effectively, but the frequency response inconsistency among channels will introduce frequency response mismatches, which will seriously degrade the signal quality. In this paper, a novel multi‐channel frequency response mismatches adaptive calibration method is proposed. The frequency response of the compensation filter is expanded into a polynomial of a digital differentiator, and the least mean square adaptive strategy is used to calibrate frequency response mismatches. It does not require measuring the channel frequency responses in advance and uses digital post‐processing technology to effectively compensate the frequency response of the multi‐channel TIADC system and improve the spurious‐free dynamic range. The experimental results verify the effectiveness of the algorithm. [ABSTRACT FROM AUTHOR]

Summary: A foreground calibration method for timing skews of the time interleaved analog‐to‐digital converter (TIADC) system is proposed in this paper. In this method, the adaptive genetic algorithm (AGA) is used to replace the traditional least mean square (LMS) method to detect the timing skews, and the variable delay lines are used to calibrate the timing skews. This method can accomplish the detection and calibration of positive and negative timing skews, and the reference channels are not required. In addition, compared with other methods, this method has higher detection speed and detection accuracy. In this paper, a four‐channel 18‐bit 1‐GS/s TIADC system is modeled, and the performance of the proposed method is further verified. The results show that the convergence speed and the calibration accuracy of this method are higher, the signal‐to‐noise ratio (SNR) of the TIADC system is improved by 65.9 dB after calibration, and this method is also effective when the frequency of the input signal is close to the Nyquist frequency. [ABSTRACT FROM AUTHOR]

As an important index of industrial oil, moisture content affects the performance of oil. With the increase of requirement to the oil quality, the measurement of ultra‐low moisture content is gradually concerned. To achieve nondestructive measurement of the moisture content in oil, this paper analyzes the principle of dielectric loss of oil‐water mixture and proposes a measurement system based on the microwave transmission method. The hardware of the system, horn antenna, and experimental device were designed and built. The system uses a subtracter circuit together with a high‐performance microwave chip and high‐precision analog‐to‐digital converter to detect 1dB microwave attenuation. The results showed that the system can measure the moisture content of 0.01%–0.8% in quenching oil and the single detection absolute error is less than ±0.05%, and the average detection absolute error of 10 detections is less than ±0.02%. This study is useful for nondestructive detection of the moisture content in oil and provides a reference for related product development. [ABSTRACT FROM AUTHOR]

This paper presents an artificially intelligent Flash ADC with enhanced resolution from 4 to 10 bits. Unlike conventional approaches, this artificial intelligence (AI)‐based architecture avoids the use of many number of comparators in the Flash ADC when the ADC's resolution changes from 4 to 10 bits. This work initially gets the digital output of a 4‐bit existing Flash ADC as a training data set and then uses these 4‐bit output bits and sends to resolution enhancement logic (REL) block to vary its resolution without increasing the hardware complexities. After simulation, it is observed that the proposed ADC is of SNR of 24.13 dB for 4‐bit Flash ADC designed in SCL 180 nm CMOS technology and increases from 36.89 to 60.70 dB for 6 to 10‐bit resolution, respectively. The sampling frequency of the proposed architecture ranges from 3.6 to 1.04 GHz for a change in resolution from 4 to 10 bits. The FoM of 235 fJ/conv‐step in the training phase is obtained, and it varies from 56 to 20.3 fJ/conv‐step in the next phase of the testing and the prediction. The estimated area of the proposed 4‐to‐10‐bit variable resolution Flash ADC is 235.23×301.67 μm2. [ABSTRACT FROM AUTHOR]

The data acquisition system is widely used in electronic measuring instruments, for example, the oscilloscope. The development direction of the oscilloscope reflects the research status and development trend of the data acquisition system. Currently, the index of oscilloscopes is progressing toward a high sampling rate, and the performance of the analog‐to‐digital converter (ADC) has become the main bottleneck to improve the sampling rate of the acquisition system. The alternate sampling technology entails multichannel low sampling rate ADCs to achieve high sampling rate data acquisition through parallel sampling and realize data reconstruction through software. The sampling clock is the most important and difficult part of the system. For ADCs with the 100‐GS/s sampling rate and 10‐bit resolution, the jitter of the sampling clock needs to be in sub‐100 fs along with multiple phases. Based on the principle of injection locking, a 150‐GS/s sampling clock is proposed in this paper, which is implemented in a 0.15‐μm GaAs process, and the 50‐GHz locking range is achieved. The measurement results show that the sampling frequency is 150 GS/s, the root mean square (RMS) jitter is 63 fs with the integrated range from 1 kHz to 10 MHz, and the phase noise can meet the sampling requirements of the 10‐bit oscilloscope, which can provide a clocking scheme for small and low‐power ultrahigh‐speed oscilloscope. [ABSTRACT FROM AUTHOR]

Summary: In this paper, a low‐power transconductor‐capacitor (Gm‐C) filter with programmable cutoff frequency is designed for electroencephalogram (EEG), electrocardiogram (ECG), and surface electromyography (sEMG) biosignals. The second‐order Butterworth low pass filter (LPF) is designed as an interface between an instrumentation amplifier (IA) and an analog‐to‐digital converter (ADC). The proposed Gm‐C filter suppresses out‐of‐band components and also plays an anti‐aliasing role. With the variable transconductance based on flipped voltage follower (FVF), the cutoff frequencies of 100 Hz, 560 Hz, and 1.5 kHz are obtained for EEG, ECG, and sEMG, respectively. This structure is highly accurate by using a robust and low‐power common mode feedback (CMFB). With 0.8 V supply voltage, the total power consumption of the filter is only 56 nW, 100 nW, and 221 nW for cutoff frequencies of 100 Hz, 560 Hz, and 1.5 kHz, respectively. The proposed Gm‐C filter is simulated in TSMC 65 nm CMOS technology and occupies an area of 0.12 mm2. The figure of merit (FOM) of the proposed filter is equal to 1.9 pW/pole. [ABSTRACT FROM AUTHOR]

Summary: The work presented in this paper aims to develop a low‐cost ultra‐wideband (UWB) radar system that has the capability to image through the wall of a human target. The proposed radar system relies heavily on a field‐programmable gate array (FPGA) platform. The Xilinx FPGA Kintex‐7 (KC705) board is employed to integrate the main functionalities of the radar system, such as the generation and acquisition of a UWB signal. The generated signal is a monocycle signal, which has an ultra‐wide bandwidth. Due to the UWB nature of this signal, the radar system achieves better penetration ability, as well as high imaging resolution. However, the major challenge of a UWB radar system lies in the stage of digitization, as it requires a high sampling rate analog‐to‐digital converter (ADC). In fact, such a chip is very expensive. Hence, to reach a high sampling resolution using a low‐cost and low‐speed ADC, an efficient sampling strategy is implemented. In contrast to other UWB sampling methods, which require a hardware delay line chip, the new sampling scheme depends only on the FPGA firmware to realize a combination of real‐time and equivalent‐time sampling, which provides better jitter performance. Finally, to demonstrate the imaging capability, experimental tests are conducted in an indoor environment while human targets are located in different places. The measurement results revealed that the proposed radar system has the ability to provide 2D images that accurately determine the location of the target. [ABSTRACT FROM AUTHOR]

Summary: In this paper, a 256 × 256 CMOS image sensor is introduced in which the pixel signals are read and converted into digital data in a completely differential mode. This technique helps to obtain pixel signals with higher linearity and accuracy compared with conventional methods. Improving the linearity and accuracy of the image sensor has a direct impact on increasing the quality of the generated images. The simulation results of the proposed pixel readout circuit show that the THD, SINAD, SNR, and SFDR are 0.45%, 47 dB, 66 dB, and 46 dB, respectively. The voltage gain of the proposed readout circuit is about 1, causing it to read the photodetector signals more accurately than the conventional methods. A full differential single‐slope ADC with a working frequency of 50 Mhz has the task of converting the pixel signal to 10 bits of digital data. The total power consumption of a column of sensors is about 80 μW. All the circuits are designed and implemented using 0.18‐μm CMOS technology in Virtuoso and simulated by the SPECTRE. [ABSTRACT FROM AUTHOR]

Touch and Display Driver Integration(TDDI) chips are widely used on smart phones and tablet PCs. Noise reduction is needed in digital raw data processing after analog‐to‐digital converters(ADC) in TDDI chips. High order digital filters are effective for digital signal noise reduction. Low time delay is required in touch panel operations. This paper proposes a method to apply an adaptive digital filter in touch panel chips with low time delay simultaneously. In this research, Signal to Noise Ratio(SNR) has been increased by an average of 7.77dB in continuous finger touch at 120Hz scan frequency, with less than 1 frame delay at touch or leave operation. [ABSTRACT FROM AUTHOR]

A classical symmetrical carrier‐based digital Average Current Mode (ACM) control has two sampling choices, peak point and valley point, to control the average inductor current. If it is employed to regulate the DC‐DC boost converter, there will be a difference in the dynamic performance at peak and valley point sampling instants because of discontinuous output voltage ripple due to Equivalent Series Resistance (ESR) of the output capacitor. Therefore, this paper investigates the effect of sampling instant on the dynamic performance of the PWM DC‐DC boost converter in consideration of capacitor ESR. The small‐signal transfer functions of a boost converter for both sampling positions are prominent to analyze each sampling impact on its dynamics. They are derived by using discrete‐time modeling. Further, the choices of sampling instant are investigated related to the RHP zero elimination, voltage stability, and peak‐to‐peak ripple current of the DC‐DC boost converter. The boost converter has improved stability performance by synchronizing the ADC sampling at starting position (valley point) of the symmetrical carrier signal, as evident by the analytical and hardware results of both sampling techniques working from 25% to 100% load working conditions. [ABSTRACT FROM AUTHOR]

The explosive growth of bandwidth demands of data center and super‐computing systems spur the appliance and development of optoelectronic‐based solutions such as micro‐ring modulator (MRM) transmitters, and advanced modulation schemes such as four‐level pulse‐amplitude modulation (PAM4). In this paper, a 4 × 25 Gb/s PAM4 MRM transmitter fabricated in 0.13 μm SiGe BiCMOS technology is presented. It consists of four‐channel MRM driver and thermal control loop. Capacitor and resistor degeneration techniques and inductor peaking techniques are adopted to expand channel bandwidth. Meanwhile, the predistortion technique is utilized to compensate for MRM nonlinearity, and auto gain control (AGC) circuits to enable the MRM driver to realize a fixed differential output swing of 3.5 Vpp. Furthermore, a thermal control method based on analog to digital converter, digital to analog converter, and logic control circuits is proposed to compensate for the temperature sensitivity of MRM. The measurement results show that the 25 Gb/s nonreturn‐to‐zero optical eye achieves an extinction ratio of 5.63 dB, and the PAM4 eye can be observed up to 40 Gb/s. [ABSTRACT FROM AUTHOR]

Summary: Direct pulse width modulated (PWM) AC–AC converters, derived from their DC–DC counterparts, serve as promising media for AC–AC power conversion because they offer benefits, such as single‐stage power conversion, absence of bulky DC links, and small footprint. In this study, a single‐phase (1−ϕ) AC–AC zeta converter was analyzed under buck, boost, and buck‐boost operations. Delta‐sigma modulation (DSM) technique, known for its simple logic implementation, excellent reference‐tracking property, robust control, and fast transient response, was employed for the load voltage control of a 1−ϕ AC–AC zeta converter. However, the conventional DSM technique relies on a fixed hysteresis band (FHB) for restricting the integrated (sigma) error (delta) between the reference and estimated control voltages within a narrow band, which causes the converter to operate at a variable switching frequency (VSF). Although VSF enhances the converter performance with low total harmonic distortion (THD) and high degree of flexibility over waveform quality, it poses serious implications such as higher switching losses, putting more strain on thermal management of switches. This paper presents a constant switching frequency‐based DSM technique based on an adaptive hysteresis band (AHB) for a 1−ϕ AC–AC zeta converter. The converter is controlled using FHB‐DSM and AHB‐DSM techniques, and a comparison is drawn between the two in terms of various performance indices. In this comparison, FHB‐DSM serves as a benchmark and an optimum switching frequency based on AHB‐DSM technique is determined, which exhibits low switching losses while maintaining the same THD limits, dynamic response, and waveform quality as that of FHB‐DSM technique. The proposed strategy was validated by simulation studies in MATLAB/SIMULINK software. Furthermore, a real‐time simulator, OPAL‐RT (OP4510), was used to validate the study with real‐time implementation. [ABSTRACT FROM AUTHOR]

Summary: This paper overcomes two key issues within radiation monitoring networks. Secure and accurate transmission of detected gamma radiation in remote areas is the first challenge. The second one is related to the robustness of transmitted signal under different fading scenarios. These issues are handled during signal transmission over worldwide interoperability for microwave access (WiMax) networks. The signals are experimentally captured using a 137Cs point source, a NaI (TI) detector, and an analog‐to‐digital converter with 16 MS/s. For the first issue, several algorithms are implemented for secure and efficient transmission of gamma‐based signals. These algorithms include encoding of captured signal, decoding, interleaving, and frequency transformation of modulated signal. Encoding and decoding of target signals are conducted using the Reed Solomon technique and convolutional encoding with a Viterbi decoder. A superior algorithm for channel interleaver using the combinational interleaving method is introduced. Fast lifting transform (FLT) is applied for transforming modulated signal into frequency domain. The results declare that CC = 1/2 with BPSK‐1/2 coding rate introduces a better BER of 0.00068. A higher SNR of 1.5 dB is accomplished by the combinational interleaving algorithm. For the second issue, several models are suggested for overcoming channel degradations under gamma, exponential, Poisson, and geometric fading. Closed‐form expressions that describe outage probability, bit error rate (BER), and symbol error rate (SER) are suggested. Geometric and gamma fading achieve respectively a lower BER of 0.18 and 0.48. These channels demonstrate similar channel performances at 3.6 dB. The proposed models are validated through comparison with published work. Finally, the proposed algorithms enable higher data rate transmission of detected 137Cs signals under higher robustness using WiMax networks. [ABSTRACT FROM AUTHOR]

This paper presents a novel procedure for detecting offset, gain, and timing skew errors in foreground calibration of time‐interleaved analog‐to‐digital converters (TI‐ADCs). An efficient peak detection scheme has been introduced, which is successfully employed to extract timing skew error. The designed method has also been extended to derive the gain and offset errors separately to form the generalized architecture. The objective is performed with the adjustment of the rational coefficient for each error. Simplicity and low hardware consumption will constitute the notable advantages of the proposed algorithm. Mathematical expressions have been provided to explain the principles. A special case in which all triple errors could exist together has also been analyzed. Then, the proposed architecture was implemented at the system level. Finally, the behavioral simulation results for a 12‐bit four‐channel TI‐ADC have been demonstrated to confirm the accuracy of the proposed algorithm. The simulation environment has consisted of the sampling frequency of 8 GHz for TI‐ADC and 1 GHz single‐tone input frequency for each channel (associated with the Gaussian noise). Based on the results, the maximum value of 77.21 dB for SFDR has been achieved after the calibration process when the average error of 9% for timing skew and 6% tolerance for gain were considered for the channels of TI‐ADC. [ABSTRACT FROM AUTHOR]

This paper presents the design, implementation, and measurements of a 4 GS/s, 8‐bit resolution, time‐interleaved (TI) analog‐to‐digital converter (ADC) comprised of 32 asynchronous successive approximation register (SAR) ADCs. The chip is fabricated in a 130 nm CMOS process. This prototype achieves the highest sampling rate and the best efficiency for a SAR TI‐ADC in the process used. An energy‐efficient hierarchical T&H architecture, ranked in a 4 × 8 structure, has been used to interleave the aforementioned high number of SAR ADCs avoiding the power hungry buffers typically used in the input signal path and/or T&H outputs. The sampling architecture includes programmable delay cells with up to 104 fs resolution to calibrate sampling time errors. Additionally, the input matching network uses an on‐chip inductance to mitigate the impact of the packaging on the analog bandwidth. An efficient SAR ADC implementation is achieved by an optimized comparator design, which allows for both, noise and asynchronous clock control, and includes background DC offset calibration. The test chip is the core of a measurement platform dedicated to the evaluation of mismatch calibration techniques for ADCs used in high speed digital communication systems. To enable this application, a 32Gb/s low‐voltage differential signaling interface is included to transmit the samples off‐chip without any decimation. The TI‐ADC achieves a peak 7.09 effective number of bits (ENOB) (5.47ENOB at Nyquist) and 1.3 GHz input bandwidth with a power consumption of 93 mW at 1.2 V. Each SAR ADC channel achieves a Walden figure of merit (FOM) of 123fJ/conv‐step and owing to the efficient interleaved architecture the full TI‐ADC achieves a peak FOM of 171fJ/conv‐step (526fJ/conv‐step at Nyquist). [ABSTRACT FROM AUTHOR]

A new quick-scanning extended X-ray absorption fine-structure (QEXAFS) system for in situ studies has been developed and tested on the general XAFS beamline at the Shanghai Synchrotron Radiation Facility. In the new system, an analog-to-digital converter (ADC) with 1 MHz sampling rate is used to acquire the detector data while one scaler is used to precisely calculate the scanning energy. Two external hardware trigger signals were adopted to synchronize the data collection of the ADC and the scaler. The software development platforms of the double-crystal monochromator control system and the new QEXAFS system have been unified with the Experimental Physics and Industrial Control System. By comparing the spectra acquired by the conventional step-by-step XAFS system with an energy range of 1200 eV at the 7.5um Cu foil K-edge, the new system demonstrates satisfactory signal-to-noise ratio and energy resolution. The previous shortcomings, including distortion of the spectrum and energy shift, have been overcome. The tests with different integration times indicated that appropriate parameters not only ensure good experimental results but also enhance the smoothness of the XAFS spectrum at high energy zones. The reliability of the new system has also been verified. [ABSTRACT FROM AUTHOR]

This letter presents an accuracy enhancement technique utilized in 16 bit fully differential successive‐approximation‐register analog‐to‐digital converters (SAR ADC). For noise performance improvement to obtain a higher ENOB, the residue measurement technique which statistically estimates the input residual error of comparator with Gaussian noise fitting is presented. The ADC digital output is compensated by the residue measurement results. It is verified in the 0.18‐μm 1P5M 5 V CMOS process. Finally, a 93.1 dB SNR and a 110.5 dB SFDR are measured operating at 1 MS/s with a 10‐kHz input tone and larger than 1‐dB SNR improvement is obtained in different chips. [ABSTRACT FROM AUTHOR]

Equivalent‐time sampling can improve measurement or sensing systems because it enables a broader frequency band and higher delay resolution for periodic signals with lower sampling rates than a Nyquist receiver. Meanwhile, a digital down‐conversion (DDC) technique can be implemented using a straightforward radio frequency (RF) circuit. It avoids timing skew and in‐phase/quadrature gain imbalance instead of requiring a high‐speed analog‐to‐digital converter to sample an intermediate frequency (IF) signal. Therefore, when equivalent‐time sampling and DDC techniques are combined, a significant synergy can be achieved. This study provides a parameter design methodology for optimal equivalent‐time sampling using DDC. [ABSTRACT FROM AUTHOR]

This letter presents a low‐power single‐slope analog‐to‐digital converter (ADC) for column‐parallel architectures. A simple and effective design technique is proposed to solve the input‐dependent power consumption problem of the conventional single‐slope ADCs. A decision‐feedback loop is implemented in the second stage of the comparator. Based on the negative‐feedback path, which is activated after the signal decision of the comparator, the input‐dependent dynamic current path in the amplifier is disabled. Furthermore, an additional low‐power design technique is proposed to save the power consumption of the ADC by optimizing the offset cancelling auto‐zero period. With the combination of the proposed techniques, the power consumption of the single‐slope ADC can be effectively saved while suppressing the dynamic current. [ABSTRACT FROM AUTHOR]

New mid‐infrared HgCdTe (MCT) detector arrays developed in collaboration with Teledyne Imaging Sensors (TIS) have paved the way for improved 10‐μ$$ \mu $$m sensors for space‐ and ground‐based observatories. Building on the successful development of longwave HAWAII‐2RGs for space missions such as NEO Surveyor, we characterize the first 13‐μ$$ \mu $$m GeoSnap detector manufactured to overcome the challenges of high‐background rates inherent in ground‐based mid‐IR astronomy. This test device merges the longwave HgCdTe photosensitive material with Teledyne's 2048×2048$$ 2048\times 2048 $$ GeoSnap‐18 (18‐μ$$ \mu $$m pixel) focal plane module, which is equipped with a capacitive transimpedance amplifier (CTIA) readout circuit paired with an onboard 14‐bit analog‐to‐digital converter (ADC). The final assembly yields a mid‐IR detector with high QE, fast readout (>85 Hz), large well depth (>1.2 million electrons), and linear readout. Longwave GeoSnap arrays would ideally be deployed on existing ground‐based telescopes as well as the next generation of extremely large telescopes. While employing advanced adaptive optics (AO) along with state‐of‐the‐art diffraction suppression techniques, instruments utilizing these detectors could attain background‐ and diffraction‐limited imaging at inner working angles <10 λ$$ \lambda $$/D, providing improved contrast‐limited performance compared with JWST MIRI while operating at comparable wavelengths. We describe the performance characteristics of the 13‐μ$$ \mu $$m GeoSnap array operating between 38 and$$ and $$ 45 K, including quantum efficiency, well depth, linearity, gain, dark current, and frequency‐dependent (1/f$$ 1/f $$) noise profile. [ABSTRACT FROM AUTHOR]

Key parameters of analog‐to‐digital converters (ADCs) are their sampling rate and dynamic range. Power consumption and cost of an ADC are directly proportional to the sampling rate; hence, it is desirable to keep it as low as possible. The dynamic range of an ADC also plays an important role, and ideally, it should be greater than the signal's; otherwise, the signal will be clipped. To avoid clipping, modulo folding can be used before sampling, followed by an unfolding algorithm to recover the true signal. Here, the authors present a modulo hardware prototype that can be used before sampling to avoid clipping. The authors' modulo hardware operates prior to the sampling mechanism and can fold higher frequency signals compared to existing hardware. The authors present a detailed design of the hardware and also address key issues that arise during implementation. In terms of applications, the authors show the reconstruction of finite‐rate‐of‐innovation signals, which are beyond the dynamic range of the ADC. The authors' system operates at six times below the Nyquist rate of the signal and can accommodate eight times larger signals than the ADC's dynamic range. [ABSTRACT FROM AUTHOR]

Purpose: Aim of this study is to assess the repeatability of radiomic features on magnetic resonance images (MRI) and their stability to variations in time of repetition (TR), time of echo (TE), slice thickness (ST), and pixel spacing (PS) using vegetable phantoms. Methods: The organic phantom was realized using two cucumbers placed inside a cylindrical container, and the analysis was performed using T1-weighted (T1w), T2-weighted (T2w), and diffusion-weighted images. One dataset was used to test the repeatability of the radiomic features, whereas other four datasets were used to test the sensitivity of the different MRI sequences to image acquisition parameters (TR, TE, ST, and PS). Four regions of interest (ROIs) were segmented: two for the central part of each cucumber and two for the external parts. Radiomic features were extracted from each ROI using Pyradiomics. To assess the effect of preprocessing on the reduction of variability, features were extracted both before and after the preprocessing. The coefficient of variation (CV) and intra-class correlation coefficient (ICC) were used to evaluate variability. Results: The use of intensity standardization increased the stability for the first-order statistics features. Shape and size features were always stable for all the analyses. Textural features were particularly sensitive to changes in ST and PS, although some increase in stability could be obtained by voxel size resampling. When images underwent image preprocessing, the number of stable features (ICC > 0.75 and mean absolute CV < 0.3) was 33 for apparent diffusion coefficient (ADC), 52 for T1w, and 73 for T2w. Conclusions: The most critical source of variability is related to changes in voxel size (either caused by changes in ST or PS). Preprocessing increases features stability to both test-retest and variation of the image acquisition parameters for all the types of analyzed MRI (T1w, T2w, and ADC), except for ST. [ABSTRACT FROM AUTHOR]

The associated discrete circuit (ADC) model for switches is widely used in electromagnetic transient simulation of power electronic system. When using ADC model, the problem of virtual power loss caused by L/C switching cannot be ignored and small time‐step (≤2 μs) is usually required to guarantee accuracy, both of which will limit the application of ADC model. To cope with this, a fractional time‐step simulation method (FTSSM) suitable for the ADC model of power electronic system is proposed. The method is derived from the compact form of electro‐magnetic transient program (EMTP) algorithm, and the simulation iteration is implemented by small‐step synthesis calculation with different fractional time‐steps, which are designed to locate the accurate switching actions. In this way, the simulation can be conducted under larger time‐step (to tens of μs) while the accuracy is still acceptable. Further analysis on time domain error and numerical stability of the FTSSM are discussed. Simulations of grid‐connected inverter system and permanent magnet synchronous motor (PMSM) driving system are done, using FTSSM and on PSCAD respectively for comparison. The results verify the accuracy of proposed FTSSM, and indicate that the FTSSM is helpful to accelerate the offline simulation and improve the real‐time simulation performance. [ABSTRACT FROM AUTHOR]

Computing‐in‐memory (CIM) is considered a feasible solution to the acceleration of multiply‐accumulate (MAC) operations at low power. The key to CIM is parallel MAC operations in the memory domain, and thus reductions in power consumption and memory‐access latency. Resistive random access memory (RRAM) can be a good candidate for the memory for CIM given its data nonvolatility, high data density, low‐latency read‐out, multilevel representation, and inherent current accumulation capability. Particularly, the last two attributes offer analog MAC operations in parallel in the memory domain. However, the fully analog MAC operation scheme causes significant power and area overheads for its peripheral circuits, particularly, analog‐to‐digital converters. To compensate for these downsides using digital processing, a method for sub‐array‐wise partial MAC operations over weight‐resistors that are optimally split to minimize power and area overheads for the peripheral circuits is proposed. The simulations performed highlight the optimal sub‐array of 4×w/2 in size. That is, weight‐splitting such that a single w‐bit weight is represented by w/2 RRAM cells, i.e., 2‐bit for each cell. For 8‐bit weights, the figure of merit (FOM) for this optimal case reaches ≈28.3× FOM for the case of no weight‐splitting. [ABSTRACT FROM AUTHOR]

This study aimed to present a comprehensive assessment of anaplastic lymphoma kinase (ALK) rearrangements evaluated by DNA/RNA‐based next‐generation sequencing (NGS) and Ventana immunohistochemistry (IHC) in patients with non‐small‐cell lung cancer (NSCLC) and to evaluate the therapeutic outcomes of ALK tyrosine kinase inhibitor (TKI) treatment. We investigated ALK gene fusions in 14,894 patients with NSCLC using Ventana IHC and NGS, including 12,533 cases detected via DNA‐based NGS and 2,361 cases using RNA‐based NGS. The overall percentage agreement (OPA), positive percentage agreement (PPA), and negative percentage agreement (NPA) were calculated when comparing the results between NGS and IHC. The therapeutic responses to ALK‐TKIs were also evaluated. In total, 3.50% (439/12,533) of specimens were NGS ALK‐positive (NGS‐p) in the DNA‐based NGS cohort and 3.63% (455/12,533) were IHC ALK‐positive (IHC‐p). The OPA of NGS was 99.60%, whereas its PPA and NPA were 92.75 and 99.86%, respectively. In the adenocarcinoma (ADC) subcohort, the PPA was 95.69%. In the RNA‐based NGS cohort, 2.20% (52/2,361) of specimens were NGS‐p and 2.63% (62/2,361) were IHC‐p. The OPA of NGS was 99.49%; its PPA and NPA were 82.26 and 99.96%, respectively. Thirteen patients with discordant results received ALK‐TKI treatment. In the seven NGS‐p/IHC‐negative (IHC‐n) patients, the overall response rate (ORR) was 85.4% (6/7) and the disease control rate (DCR) was 100%. In the six NGS‐negative/IHC‐p patients, the ORR was 66.7% (4/6) and the DCR was 100%. In summary, a high concordance of ALK gene fusion detected via NGS and IHC was observed in this study. DNA‐based NGS had a higher OPA, PPA, and PPA in the ADC subcohort, whereas RNA‐based NGS had a higher NPA. Overall, the results suggest that the combination of NGS and IHC can improve the accuracy of ALK fusion detection; hence, a result determination algorithm for clinical detection of ALK gene fusion was also proposed. [ABSTRACT FROM AUTHOR]

A 12‐bit self cascode capacitor compensated (SC3) partial segmented current steering digital to analog converter (DAC) is proposed and implemented in standard 180‐nm CMOS technology. The effect of the output capacitance at a higher frequency of operation is analyzed. Based on the analysis, a self cascode transistor is connected on the top of the differential switch with an "always‐on" biasing without compromising the voltage headroom. Besides, a compensation capacitor is also used at the output to improve spur free dynamic range (SFDR), which is obtained as 108 dB when sampled at 800 MS/s. The proposed architecture also offers high output impedance by more than 10 times compared with the cascode device. The proposed design also enhances the bandwidth of the circuit and is obtained to be 4 GHz with a power supply rejection ratio (PSRR) of 43 dB. It also has a total harmonic distortion (THD) of <3% up to input power of −4 dB and is also insensitive to process variations with a sensitivity of <0.5%. [ABSTRACT FROM AUTHOR]

The authors present a dither‐less background digital bit weights calibration method for split‐capacitor digital‐to‐analog converter (CDAC) successive approximation register (SAR) analog‐to‐digital converters (ADCs) to improve non‐linearities caused by capacitor mismatch and bridge‐capacitor inaccuracy errors in a split‐CDAC. By using a digital pseudo‐random number (PN) generator and paired comparators with opposite offsets, a dither‐less background calibration quickly reaches the target signal‐to‐noise‐and‐distortion ratio (SNDR) within 5 × 104 samples for various process uncertainties. The simulated performance using a behavioural 6‐bit + 6‐bit ADC with 1‐bit redundancy for various random offset and capacitor mismatches shows that the SNDR increases from 45.7 to 65.7 dB after the calibration. [ABSTRACT FROM AUTHOR]

Summary: This study presents four designs for a true random number generator (TRNG) for Cypress programmable system‐on‐chip (SoC) (PSoC) devices, whose entropy source is the thermal noise of resistors. The first design includes a ΔΣ analog‐to‐digital converter (ADC) with two external resistors of 6 MΩ, where the resolution was set to 16 bits. The second, third, and fourth designs adopt the internal resistors of a programmable gain amplifier (PGA) as a noise source. The second design adopts a single‐stage PGA (gain 50) with a ΔΣ ADC, while the third design adopts a two‐stage PGA (gain 50 × 50) with a ΔΣ ADC. The fourth design adopts a trans‐impedance amplifier (TIA) with a ΔΣ ADC. All four designs have passed the National Institute of Standards and Technology (NIST) test suite. [ABSTRACT FROM AUTHOR]

The fully passive noise shaping (NS) successive approximation register (SAR) analog-to-digital converters (ADCs) are simple, operational transconductance amplifier (OTA) free and scaling friendly. Previous passive NS-SAR ADCs rely on the multi-path-input comparator or capacitors stacking to realize the passive gain for compensating the signal attenuation during passive integration. However, the former causes high comparator power consumption, and the latter suffers from additional signal attenuation due to the parasitics and is hard to extend to high-order systems. This work proposes a new fully passive NS-SAR technique, it can realize 2 × gain with a simple structure, leading to the reduced comparator power, and less parasitics. This technique is also easy to extend to high-order NS-SAR ADCs. [ABSTRACT FROM AUTHOR]

This article presents a design of a VCO‐based ADC based on n‐type metal oxide thin‐film transistor (TFT). The TFTs are fabricated on a glass substrate using Indium Zinc Oxide technology. The VCO‐based ADC consists of a VCO, a level shifter and a sampling circuit, while the VCO is composed of a charge‐discharge cell and an inverter chain. The ADC has a 1.464 mm 2 area, 0.89 mW power consumption, an output frequency range of 1.41 KHz/V tuning sensitivity, 1.8% maximum linear error and achieves a SNDR of 34.2 dB in the case of an input signal of 1.5 Hz and a sampling rate of 20 S/s. [ABSTRACT FROM AUTHOR]