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The memory module is a semiconductor product fabricated by mounting several memory chips on a printed circuit board. In the module test, which is the final step in the memory module manufacturing process, the memory module is tested if it properly functions in the end-user system environment. Then, the chips in the memory module are individually checked for defects to guarantee that the quality matches consumers’ expectations. In this study, we propose a framework to predict which chips are defective in module tests using wafer and package test data. However, several challenges must be overcome. First, two different data modalities (i.e., tabular and image data) exist, which influence defect prediction differently for different chips. Second, the module test results are highly imbalanced, with a very low defect rate. To address these challenges, we use a multimodal fusion model that integrates the two different modalities by dynamically evaluating the informativeness of each modality. In addition, we adopt a technique to modify the loss function to be Fisher consistent to minimize the balanced error rate. We demonstrate that the proposed framework can effectively predict chip-level defects in module tests using a real dataset collected from a global semiconductor manufacturing company. [ABSTRACT FROM AUTHOR]

A wafer bin map (WBM) represents the locational information of defective chips on the wafer. The spatial correlation of defects on the wafer provides crucial information for the root cause diagnosis of defects in wafer fabrication. The spatial correlation is classified as a defect pattern for efficient diagnostics. A defect pattern taxonomy should be defined in advance for coherent classification of defect patterns. Various taxonomies are used in previous studies, but they share common limitations in that the differentiation among defect patterns is unclear, the set of predefined defect patterns is insufficient, and they cannot accommodate newly-emerged defect patterns. A concept of spatial dimension-based defect pattern taxonomy and its development procedure are proposed. Defect patterns are defined by three spatial dimensions, namely, Shape , Size , and Location. The development procedure is applied to a major NAND flash memory semiconductor manufacturer for two years. Results show that spatial dimension-based taxonomy can improve the performance of the defect pattern classification system by alleviating common existing limitations. Moreover, meaningful defect patterns for diagnostics are retained through the engineers' involvement in the development procedure. [ABSTRACT FROM AUTHOR]