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Summary: A high frequency resolution digitally controlled oscillator (DCO) is proposed for wireless transceivers, in which the scheme adopts an optimized cascaded differential switched‐capacitor (SC) ladder and a low‐coupled eight‐shaped transformer. The frequency resolution is further improved by the low electromagnetic coupling effect between the primary and secondary coils of the on‐chip transformer, thus reducing quantization noise and phase noise. An eight‐shaped transformer designed using two coils cross‐connected each other is adopted to reduce the magnetic coupling and frequency pulling. The proposed DCO is implemented in a TSMC 180‐nm CMOS process, and a tuning range of 36.7% from 3.83 to 5.55 GHz with a frequency resolution of 17 kHz is achieved. The phase noise is −120.29 dBc/Hz at 1 MHz offset from the 3.83 GHz carrier frequency. The DCO consumes 9.26 mA from a 1.8 V supply, while the figure of merit with tuning range is −191 dBc/Hz. The chip size is 0.294 mm2. [ABSTRACT FROM AUTHOR]

Analog arithmetic operations are the most fundamental mathematical operations used in image and signal processing as well as artificial intelligence (AI). In‐memory computing (IMC) offers a high performance and energy‐efficient computing paradigm. To date, in‐memory analog arithmetic operations with emerging nonvolatile devices are usually implemented using discrete components, which limits the scalability and blocks large scale integration. Here, a prototypical implementation of in‐memory analog arithmetic operations (summation, subtraction and multiplication) is experimentally demonstrated, based on in‐memory electrical current sensing units using spin‐orbit torque (SOT) devices. The proposed structures for analog arithmetic operations are smaller than the state‐of‐the‐art complementary metal oxide semiconductor (CMOS) counterparts by several orders of magnitude. Moreover, data to be processed and computing results can be locally stored, or the analog computing can be done in the nonvolatile SOT devices, which are exploited to experimentally implement the image edge detection and signal amplitude modulation with a simple structure. Furthermore, an artificial neural network (ANN) with SOT devices based synapses is constructed to realize pattern recognition with high accuracy of ≈95%. [ABSTRACT FROM AUTHOR]

—In this paper, a class-F 23 VCO using nonlinear-capacitance transforming technique to simultaneously achieve low phase noise and a wide tuning range is proposed. The phase noise degradation due to the nonlinearity of the switched capacitor in the class-F 23 oscillator is analyzed and quantitatively derived. The phase noise contributed by the nonlinear capacitance can be suppressed by using the proposed nonlinear-capacitance transformation technique. In order to achieve low phase noise over a wide bandwidth, the asymmetric-toggling method is utilized to achieve optimal capacitance ratios across the entire frequency range. Implemented in a 40-nm CMOS process, the proposed oscillator exhibits 41.2 % tuning range from 2.58 GHz to 3.92 GHz while consuming 13.8 mW–14.9 mW power dissipation. The phase noises at 2.58 GHz and 3.92 GHz oscillation frequencies are −136.4 dBc/Hz and −129.6 dBc/Hz at 1-MHz offset. The minimum phase noise is −157.2 dBc/Hz at 10 MHz offset, corresponding to an FoM of 194.1 dBc/Hz and FoM T of 206.4 dBc/Hz. [ABSTRACT FROM AUTHOR]

This paper presents a fractional- N all-digital phase-locked loop (ADPLL). A 4-bit multi-delay line time-to-digital converter (MDL-TDC) using path selection technique is proposed to achieve a 4-ps resolution with 0.24-mW power consumption at 52 MS/s. A TDC offset calibration method is used to eliminate TDC metastability. An isolated constant-slope digital-to-time converter (ICS-DTC) is utilized to cancel the quantization noise (Q-noise) and achieve true-fractional delay. By tuning DTC compensation, spur and Q-noise are suppressed by 14 dB. To speed up the locking process of the ADPLL, a counter-based coarse PLL is integrated to monitor and compensate for large frequency and phase jump while consuming almost zero power. The proposed ADPLL is implemented in a 40-nm standard CMOS process, occupying a silicon area of 0.36 mm2. When TDC offset calibration is turned on, the in-band noise is suppressed by 20 dB. The measured results show 0.78-ps rms jitter and −40-dBc in-band fractional spur are achieved, corresponding to a figure of merit (FOM) of −235 dB. [ABSTRACT FROM AUTHOR]