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This paper proposes a modified Schmitt-trigger (ST)-based single-ended 11 T (MST11T) SRAM cell. The proposed cell is best suited to ultra-low voltage applications. Two ST-based cross-coupled inverters comprise the storage cell of the proposed MST11T bit cell. In comparison with conventional inverters, ST-based inverters have sharp voltage transfer characteristics. As a result, the proposed bit cell's stability performance increases. The proposed SRAM cell's leakage power consumption is reduced because of the use of stacked N-type transistors. For the read operation of the proposed bit cell, the read decoupled technique is used. As a result, the read static noise margin (RSNM) has greatly improved. The proposed bit cell's write static noise margin (WSNM) is increased by adopting feedback-cutting methodology. The performance of the proposed bit cell is compared with that of conventional 6 T, conventional 8 T, Schmitt-trigger 10 T (known as ST2), modified PMOS-PMOS-NMOS-based cell core 10 T (MPPN10T), feedback-cutting 11 T (FC11T), Schmitt-trigger 11 T (ST11), and Schmitt-trigger 12 T (ST12T) cells. According to the simulation results, the proposed MST11T SRAM cell has RSNM of 2.42, 1.18, 1.71, 1.30, and 1.80 times higher when compared to 6 T, FC11T, ST2, MPPN10T, and ST12T, respectively. The WSNM of the proposed bit cell has been increased by 1.56, 2.44, 1.28, 1.71, 1.35, 1.52, and 1.02 times, respectively, over 6 T, 8 T, ST2, MPPN10T, FC11T, ST11T, and ST12T. Furthermore, the suggested cell has a read delay that is 1.32, 1.79, and 1.53 times lower than ST11T, FC11T, and ST12T, respectively. The proposed bit cell has a write delay that is 1.14 and 1.63 times lower than FC11T and ST11T, respectively. The proposed MST11T bit-cell consumes 3.74, 1.56, 4.59, 5.38, and 4.83 times less leakage power than the 8 T, ST2, MPPN10T, FC11T, and ST12 bit-cells, respectively. When compared to 8 T/ST2/MPPN10T/ST12T at 0.2 V supply voltage, the enhanced facts incur a 4.87/3.79/3.78/1.97 penalty in write delay. The figure of merit (FOM) is derived as a result of this extensive access to the revolutionary SRAM cell performance, i.e., offering greater values at a 0.2 V DC supply voltage. In addition, the paper examines the impact of manufacturing process and temperature changes on MST11T cell enactment, as well as the circuit robustness using HSPICE with 7-nm FinFET technology. [ABSTRACT FROM AUTHOR]

This paper presents a high-stability low-power 10 T (HSLP10T) sub-threshold SRAM cell with single-ended operations. The HSLP10T cell uses a decoupled read path, formed by a transmission gate and a dynamic inverter, thereby, resulting in read stability improvement. In addition, it employs a feedback-cutting transistor to facilitate the write operation, which increases writability. Due to single-ended operations, direct-write on complementary node, floated bitline, and use of more p-type transistors, the power consumption reduces in the proposed cell. Simulated results in the 7-nm FinFET technology indicate that at a 300 mV supply voltage, the read stability/writability of the proposed HSLP10T cell is 2.06X/1.31X as that of the conventional 6 T cell. Moreover, the dynamic/leakage power consumption is reduced by 1.82X/2.92X when compared with the conventional 6 T SRAM. The proposed HSLP10T SRAM bitcell has a layout area of 0.047 µm2, which is 1.67 × larger than the conventional 6 T SRAM. However, the highest ON-to-OFF currents ratio related to the proposed design compensates for this area overhead by connecting more number of cells to the same bitline in the columns of the SRAM array. Moreover, the minimum operation voltage is reduced by 48.28 % using proposed design compared to the conventional 6 T SRAM. [ABSTRACT FROM AUTHOR]