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The multi-component glass system has a composition of 10K2O–10ZnO–55 B2O3–(25–x)V2O5–xBi2O3 (x = 4, 5, 7.5, 9, 10 mol%) are synthesized by the melt-quenching method. Using X-ray diffraction examination, the amorphous phase in the material was confirmed. The physical characteristics of the produced compositions are examined using density (D) and molar volume (Vm). Calculations of physical properties showed that adding Bi2O3 from 4 to 10 mol% increased the glass density from 2.7878 to 3.3617 g cm−3 and decreased the molar volume from 40.4196 to 38.5895 cm3/mol. Studies of glass samples using the FTIR show bands of absorption for oxides in different structural groups. Octahedral [ BiO 6 ], [ BO 4 ], and tetrahedral [ BO 3 ] structural units are observed in the present glass matrices. The cutoff wavelength ( λ C ), and optical band gap energy were determined using UV absorption spectra. The increase in non-bridging oxygens can be linked to the decrease in optical band gap energy ( E opt ) (direct and indirect) and the increase in cutoff wavelength with an increase in Bi2O3 content. This is attributed to the existence of bismuth ions and the creation of non-bridging oxygens. Besides that, the values of optical parameters, viz., optical electronegativity, refractive index, and molar refractivity, are calculated. The metallization criterion values are less than 1 and the glass samples exhibit an increased tendency towards metallization. Both the conductivity and the dielectric constant increase with the rise in Bi2O3 content, however, the dielectric loss and the impedance reduce. The behavior and values of conductivity for the studied glasses reveal the semiconducting properties of all glass samples. These results suggest that the produced glass samples may be employed as amorphous semiconductors in electronics and memory switching devices. [ABSTRACT FROM AUTHOR]

...-ispotty-byte error correcting codes over Zq [7] are non-binary codes generalizing the binary irregular-spotty-byte codes [3] suitable for semiconductor memories in which a word is divided into irregular bytes not necessarily of the same length. The distance between distinct words is measured in terms of newly defined ... - metric function [7]. In this paper, we present the code construction methods of ...-ispotty-byte error correcting codes in terms of their parity check matrix. [ABSTRACT FROM AUTHOR]

With the development of electronic technology, semiconductor memory is gradually shifting toward smaller area with less power consumption. SOT-MRAM is one of the competitive substitutes for DRAM and SRAM due to its superior endurance and switching speed. In contrast to STT-MRAM, the separation of read and write routes allows SOT-MRAM to have a lower error rate and higher lifetime, but this comes at the expense of the memory density. In recent years, vertical integrated circuits have relied on TSV to complete 3D stacking to ease the pressure of Moore's Law on scaling circuits. SOT-MRAM can take advantage of 3D stacking to reduce power and latency. More importantly, the density of SOT-MRAM can be improved at the same time. In the paper, simulation is conducted based on DESTINY, with the TSV model supplemented to NVSIM to evaluate the performance of MRAM 3D structures. The 3D SOT-MRAM structure in DESTINY can be implemented with a bus layer and interconnect structure between layers, which greatly reduces the expense of area. However, the 3D structure requires a more complex interconnect structure to truly meet the requirements of high density. For this reason, 3D model of unit interconnection using TSV is presented in the paper. Memory has several components, of which the memory array is the one with the largest area share. This paper explores the spatial structure of the array and proposes a new model which allows more complex interconnect structures to be accomplished on the same area. [ABSTRACT FROM AUTHOR]

In this theoretical study, we explore the use of quantum code-based memories to enhance the lifetime of qubits and exceed the break-even point, which is critical for the implementation of fault-tolerant quantum computing. Specifically, we investigate the quantum phase-flip repetition code as a quantum memory and theoretically demonstrate that it can preserve arbitrary quantum information longer than the lifetime of a single idle qubit in a dephasing-time-limited system, e.g. in semiconductor qubits. Our circuit-based analytical calculations show the efficiency of the phase-flip code as a quantum memory in the presence of relaxation, dephasing, and faulty quantum gates. Moreover, we identify the optimal repetition number of quantum error correction cycles required to reach the break-even point by considering the gate error probabilities of current platforms for quantum computing. Our results provide guidelines for developing quantum memories in semiconductor quantum devices. [ABSTRACT FROM AUTHOR]

Soft errors are the primary concern in space and terrestrial integrated circuit applications. When a charged particle from space collides with a scaled memory circuit, a transient pulse is generated across the sensitive storage node, causing a bit flip throughout the storage nodes. This bit flip is stated as a soft error, which affects the semiconductor memory architecture's stability and reliability. This paper presents a 10 T SRAM (STS-10 T) cell that mitigates soft error challenges even at space temperature. To demonstrate the relative performance of the STS-10 T, existing radiation-hardened memory cells, such as the Quatro-10 T, PS10T, NS-10 T, RHBD-10 T, 10 T-SRAM, RHMD-10 T, QUCCE-10 T, and SIS-10 T, were evaluated. The read stability of the proposed STS-10 T memory cell is 2.6x/ 3x/ 1.5x/ 1.4x/ 1.25x/ 1.6x/ 2.03 × greater than that of the existing Quatro-10 T/ NS-10 T/ PS-10 T/ RHBD-10 T/ RHMD-10 T/ QUCCE-10 T/ SIS-10 T memory cells, respectively. Moreover, 1.48x/ 1.17x/ 1.18x/ 1.4x/ 1.01x/ 1.27x/ 1.45x/ 1.43 × greater write ability than Quatro-10 T/ NS-10 T/ PS-10 T/ RHBD-10 T/ 10 T-SRAM/ RHMD-10 T/ QUCCE-10 T/ SIS10T. In addition, when the supply voltage is at 1 V, the read and write access time, hold power, and critical charge is also improved. [ABSTRACT FROM AUTHOR]

The eutectic structure of metals and ceramics is the result of a self‐organization phenomenon in which multiple solid phases solidify with an ordered structure from a liquid phase. Hence, a melt‐solidification process was the only way to generate ordered structures in a ceramic eutectic system. Here, we prepared ordered structures of Y3Al5O12 (YAG)–Al2O3 composites via chemical vapor deposition in the YAG–Al2O3 eutectic system. Spatially periodic YAG rod and lamellar structures were generated in an alumina matrix homoepitaxially grown on the sapphire substrates on the Al2O3‐rich side of the eutectic composition, whereas α‐Al2O3 rod and lamellar structures were generated in a YAG matrix on the Y2O3‐rich side. The results reveal that the pattern formation of ordered structures in a ceramic eutectic system can occur not only during in the melt‐solidification process but also during the vapor deposition process. The Ce3+‐doped YAG–Al2O3 composite film converts some of the blue light into yellow light, allowing some of it to pass through, and emitting white light. The Eu3+‐doped YAG–Al2O3 composite film can be utilized as a scintillation screen for a high‐resolution X‐ray imaging test to see though a semiconductor storage device. [ABSTRACT FROM AUTHOR]

The next‐generation semiconductor memories are essentially required for the advancements in modern electronic devices. Ferroelectric memories by HfO2‐based ferroelectric thin films (FE‐HfO2) have opened promising directions in recent years. Nevertheless, improving the polarization switching speed of FE‐HfO2 remains a critical task. In this study, it is demonstrated that the composition‐graded Hf1‐xZrxO2 (HZO) ferroelectric thin film has more than two times faster polarization switching speed than the conventional composition‐uniform one. Meanwhile, it has excellent ferroelectricity and improved endurance characteristics. It is also discovered that when the HZO thin film has a gradient composition, the polarization‐switching dynamics shifts from the nucleation‐limited‐switching mechanism to the domain‐wall growth mechanism. Moreover, the transition of switching dynamics is responsible for the faster speed and better endurance of the composition‐graded HZO thin film. These findings not only reveal the physical mechanisms of this material system but also provide a new strategy for memory devices having faster speed and higher endurance. [ABSTRACT FROM AUTHOR]

The memory module is a semiconductor product fabricated by mounting several memory chips on a printed circuit board. In the module test, which is the final step in the memory module manufacturing process, the memory module is tested if it properly functions in the end-user system environment. Then, the chips in the memory module are individually checked for defects to guarantee that the quality matches consumers’ expectations. In this study, we propose a framework to predict which chips are defective in module tests using wafer and package test data. However, several challenges must be overcome. First, two different data modalities (i.e., tabular and image data) exist, which influence defect prediction differently for different chips. Second, the module test results are highly imbalanced, with a very low defect rate. To address these challenges, we use a multimodal fusion model that integrates the two different modalities by dynamically evaluating the informativeness of each modality. In addition, we adopt a technique to modify the loss function to be Fisher consistent to minimize the balanced error rate. We demonstrate that the proposed framework can effectively predict chip-level defects in module tests using a real dataset collected from a global semiconductor manufacturing company. [ABSTRACT FROM AUTHOR]

We fabricate top-gate transistors on the three-layer molybdenum disulfide (MoS2) with three, two, and one layers in the source and drain regions using atomic layer etching (ALE). In the presence of ALE, the device at zero gate voltage can exhibit high and low levels of drain current under the forward and reverse gate bias, respectively. The hysteresis loop on the transfer curve of transistor indicates that two distinct charge states exist in the device within a range of gate bias. A long retention time of the charge is observed. Unlike conventional semiconductor memories with transistors and capacitors, the two-dimensional (2D) material itself plays two parts in the current conduction and charge storage. The persistent charge storage and memory operation of the multilayer MoS2 transistors with thicknesses of a few atomic layer will further expand the device application of 2D materials with reduced linewidths. [ABSTRACT FROM AUTHOR]

The study considers the impact of the environmental contamination by the electromagnetic radiation of electron beam generator and high-energy radioactive source on the memory components. Electron beam generator can be used for injecting particle energy into the plasma of the fusion system based on a Marx generator, while radioactive source as a simulator of high-energy ionizing radiation that can be caused by the neutron-induced activation of plasma surrounding structures or released from deuterium-tritium fusion reaction. The effects of gamma radiation of high-energy radioactive source and electric field of the electron beam generator on EPROM and EEPROM semiconductor computer memory, were investigated. An older memory types were deliberately chosen for the reason that their more robust construction will better protect them from the effects of ionizing and non-ionizing radiation. The results obtained under well-controlled conditions show a high degree of non-resistance of the semiconductor technology to the expected electromagnetic pollution of the electron beam generator and high-energy radioactive source. This conclusion raises doubts on the possibility of simultaneous application of electron beam generator, consequently fusion system and nanotechnologies with the increasing need for miniaturization of electronic components. [ABSTRACT FROM AUTHOR]

As a nanoscale semiconductor memory device, a ferroelectric memristor has promising prospects to break through the von Neumann framework in terms of artificial synaptic function, information processing, and integration. This study presents the fabrication of Li0.09Bi0.91FeO3 as the functional layer for a memristor device based on the Si substrate, enabling the integration of silicon complementary metal oxide semiconductor technology. In addition, it exhibits bipolar resistance switching characteristics in a direct current mode and can rapidly achieve stable conductance tunability at higher frequencies through the applied pulse for biosynapse simulation. More importantly, multiple devices are connected into electrical circuits to realize storage functions with information processing and programmable characteristics. This work paves the way for near-future applications of ferroelectric memristors in information processing. [ABSTRACT FROM AUTHOR]

Since research on artificial intelligence has begun receiving much attention, interest in efficient hardware that can process a complex and large amount of information has also increased. The existing von Neumann computing architecture has significant limitations in terms of speed and energy efficiency. Volatile memristors are the most promising among several emerging memory semiconductor devices, because they have various features suitable for neuro-inspired applications. Therefore, a comprehensive review of volatile memristors is urgently needed for future research. Herein, we present the physical interpretation and latest research trends of the switching mechanisms of volatile memristors. We also review diverse promising applications using volatile memristors. In particular, we focus on selectors for array structures, synaptic devices for neuromorphic engineering, imitation of nociceptors, and reservoir computing for time-dependent input data processing. Finally, we discuss the future directions of volatile memristors and their applications. [ABSTRACT FROM AUTHOR]

In the fast-paced development of life in today's society, the use of ECG signals is not only used in the medical direction to scan patients; portable ECG signal acquisition tools can collect and analyze the corresponding ECG signals in time and respond to the wearer in time, so that the user can make timely adjustments or seek medical treatment in time to avoid a malignant situation that occurs. For people in sports, the collection of ECG signals is more helpful to the arrangement and estimation of training conditions. Based on nonvolatile memory technology, data will not be lost when the computer is turned off or suddenly or unexpectedly shut down. This research puts forward the design of an antiexercise ECG monitoring system that collects ECG signals for a group that is in the process of exercise. Use mathematical calculation system to classify, and conduct in-depth analysis of the reasons for poor anti-interference ability, and use the original denoising algorithm calculation as the basis to adapt to the dynamic situation in the opposite situation to the normal ECG signal acquisition in the static state. The collection is modified from the original basis. This research proposes an improved scheme for multichannel acquisition. Chips of semiconductor memory devices based on nonvolatile memory are embedded in mobile devices for use. The experimental results in this paper show that the comparison experiment ratio of collecting ECG signals from the sixth, third, fourth, and fifth directions can effectively reduce the mean square error (MSE), and the error of channel 6 is directly from 0.1598. It is down to 0.00143. Several other items showed a significant decrease. It shows that the anti-interference ability of the ECG monitoring system can be further enhanced by increasing the number of collection terminals. [ABSTRACT FROM AUTHOR]

To lower the charge leakage of a floating gate device and improve the operation performance of memory devices toward a smaller structure size and a higher component capability, two new types of floating gates composed of pn-type polysilicon or np-type polysilicon were developed in this study. Their microstructure and elemental compositions were investigated, and the sheet resistance, threshold voltages and erasing voltages were measured. The experimental results and charge simulation indicated that, by forming an n-p junction in the floating gate, the sheet resistance was increased, and the charge leakage was reduced because of the formation of a carrier depletion zone at the junction interface serving as an intrinsic potential barrier. Additionally, the threshold voltage and erasing voltage of the np-type floating gate were elevated, suggesting that the performance of the floating gate in the operation of memory devices can be effectively improved without the application of new materials or changes to the physical structure. [ABSTRACT FROM AUTHOR]

With the upcoming trend of Big Data era, some new types of memory technologies have emerged as substitutes for the traditional Si-based semiconductor memory devices, which are encountering severe scaling down technical obstacles. In particular, the resistance random access memory (RRAM) and magnetic random access memory (MRAM) hold great promise for the in-memory computing, which are regarded as the optimal strategy and pathway to solve the von Neumann bottleneck by high-throughput in situ data processing. As far as the active materials in RRAM and MRAM are concerned, organic semiconducting materials have shown increasing application perspectives in memory devices due to their rich structural diversity and solution processability. With the introduction of metal elements into the backbone of molecules, some new properties and phenomena will emerge accordingly. Consequently, the RRAM and MRAM devices based on metal-containing organic compounds (including the small molecular metal complexes, metallopolymers, metal–organic frameworks (MOFs) and organic–inorganic–hybrid perovskites (OIHPs)) have been widely explored and attracted intense attention. In this review, we highlight the fundamentals of RRAM and MRAM, as well as the research progress of the applications of metal-containing organic compounds in both RRAM and MRAM. Finally, we discuss the challenges and future directions for the research of organic RRAM and MRAM. [ABSTRACT FROM AUTHOR]

This paper considers a new model of error control codes for semiconductor memories consisting of RAM chips not necessarily of the same size. The information stored on a chip corresponds to a variable length byte and thus byte length is not same in this case and varies from chip to chip. The variable length byte is termed as a "general byte" or simply a "g-byte". The code presented in this paper are capable of correcting all single g-byte errors. [ABSTRACT FROM AUTHOR]

A wafer bin map (WBM) represents the locational information of defective chips on the wafer. The spatial correlation of defects on the wafer provides crucial information for the root cause diagnosis of defects in wafer fabrication. The spatial correlation is classified as a defect pattern for efficient diagnostics. A defect pattern taxonomy should be defined in advance for coherent classification of defect patterns. Various taxonomies are used in previous studies, but they share common limitations in that the differentiation among defect patterns is unclear, the set of predefined defect patterns is insufficient, and they cannot accommodate newly-emerged defect patterns. A concept of spatial dimension-based defect pattern taxonomy and its development procedure are proposed. Defect patterns are defined by three spatial dimensions, namely, Shape , Size , and Location. The development procedure is applied to a major NAND flash memory semiconductor manufacturer for two years. Results show that spatial dimension-based taxonomy can improve the performance of the defect pattern classification system by alleviating common existing limitations. Moreover, meaningful defect patterns for diagnostics are retained through the engineers' involvement in the development procedure. [ABSTRACT FROM AUTHOR]

Spinel ferrites have a significant impact due to its physical and chemical properties. The solgel route has been employed in the present work, for achieving single phase nano-crystalline cobalt ferrites. All these samples were annealed with different temperatures from 600 °C to 900 °C in a muffle furnace. The FCC spinel structure of nanoparticles has been confirmed by powder x-ray diffraction (XRD) studies that demonstrate formation of crystalline size at various temperatures from 11-15 nm. The Raman spectroscopy revealed the characteristic absorption bands in 100 cm-1 to 700 cm-1 range where the graphs show five absorption bands and they confirmed the characteristic feature of spinel structure. With the help of Maxwell Wagner model, dielectric characterization has been carried out within a frequency range from 20 Hz to 20 MHz where dielectric parameters are found decreased with increasing the applied frequency. The alternating current conductivity phenomena increases with higher frequency ranges and show plane behavior in lower frequency ranges. The impedance mechanism, real and imaginary parts show decreasing trend on account of grain boundary activity. Interfacial polarization understood with the help of peaks obtained from the imaginary modulus pattern. These cobalt ferrite nanoparticles (CoFe2O4 NPs) are suitable to use in microwave devices, high frequency equipment, semiconductor devices and high storage media applications revealed by the dielectric studies. [ABSTRACT FROM AUTHOR]

In this study, we present programming speed enhancement in amorphous oxide semiconductor memory thin-film transistor (TFT). We developed a nonvolatile memory transistor based on InZnSnO back-channel-etch TFT with InGaZnO charge storage layer inserted between gate insulators. We proposed double-gate (DG) and body-contacted (BC) memory structure to improve memory erase speed, which is the most important issue in oxide memory TFTs. DG memory did not show sufficient improvement due to large voltage drop in second gate insulator. BC memory, which can control back-channel potential directly, showed significant improvement on memory program/erase speed. [ABSTRACT FROM AUTHOR]

The present day electronic gadgets have semiconductor memory devices to store data. The static random access memory (SRAM) is a volatile memory, often preferred over dynamic random access memory (DRAM) due to higher speed and lower power dissipation. However, at scaling down of technology node, the leakage current in SRAM often increases and degrades its performance. To address this, the voltage scaling is preferred which subsequently affects the stability and delay of SRAM. This paper therefore presents a negative bit-line (NBL) write assist circuit which is used for enhancing the write ability while a separate (isolated) read buffer circuit is used for improving the read stability. In addition to this, the proposed design uses a tail (stack) transistor to decrease the overall static power dissipation and also to maintain the hold stability. The comparison of the proposed design has been done with state-of-the-art work in terms of write static noise margin (WSNM), write delay, read static noise margin (RSNM) and other parameters. It has been observed that there is an improvement of 48%, 11%, 19% and 32.4% in WSNM while reduction of 33%, 39%, 48% and 22% in write delay as compared to the conventional 6T SRAM cell, NBL, V DD collapse and 9T UV SRAM, respectively. [ABSTRACT FROM AUTHOR]

ULTRARAM™ is a III–V semiconductor memory technology which allows non-volatile logic switching at ultra-low energy (per unit area). This is achieved by exploiting triple-barrier resonant tunnelling (TBRT) through a series of InAs/AlSb heterojunctions specifically engineered for this purpose. Electrons tunnelling through the barriers at low bias are trapped in a floating gate, in which the presence or absence of charge defines the memory logic. Here, we report detailed non-equilibrium Green's functions simulations of the InAs/AlSb TBRT heterostructure, which is the principal source of ULTRARAM™'s extraordinary performance benefits. The effects of variations to the heterostructure layer thickness are investigated for performance optimization, and for assessing growth and process tolerances for commercial implementation on 12″ Si wafers. Trade-offs between power, speed, logic disturbance and data retention time are identified. Importantly, most one monolayer alterations to the tunnelling region show the required characteristics for ULTRARAM™ memory operation, thus some tolerance in any future commercial fabrication process is identified. [ABSTRACT FROM AUTHOR]

As a promising alternative to dynamic RAM, phase change memory (PCM) suffers from limited write endurance. Therefore, many research proposals on PCM security or reliability have focussed on the possible threat of wear‐out attacks from malicious applications. However, it is also found that the non‐volatile nature and the programming behaviour of PCM bring other security challenges to the memory system. The authors examine the potential risk of information leakage and theft in memory management for PCM‐based cloud server or multitenant systems. By observing the influence of process variation (PV) on PCM cell programming, they propose a fast and efficient in‐memory data obfuscation mechanism to defend against memory attacks or information leakage during page reallocation mandated by OS. With the capabilities of in‐memory data randomisation, the proposed SecuRAM avoids the long write latency of PCM cells to erase the content, and achieves higher data initialisation efficiency than conventional software solutions. Second, the proposed SecuRAM also provides a novel solution of fast in‐memory hardware fingerprinting and random number generation, which are common and essential security functions in encryption or access authentication to protect confidential memory data from attackers. Two novel techniques are proposed to generate signatures and random numbers: the first is based on partial programming, which works in the same way as bulk data randomisation; the second is loop‐counting, which is an overhead‐free method by reusing the cell programming mechanism in iterate‐write PCM devices. Through evaluation, SecuRAM shows a much better performance and energy‐efficiency than conventional measures for PCM memory. [ABSTRACT FROM AUTHOR]

BACKGROUND: Traditionally, X-ray systems for capturing moving objects consist of a continuous X-ray source and a detector that operates at a predetermined frame rate. OBJECTIVE: This study investigates the possibility of using pulsed X-ray source with an inductive energy storage device and a semiconductor opening switch for shooting moving objects. METHODS: The study uses a high-voltage pulse generator that has the following parameters namely, the pulse voltage amplitude up to 320 kV, the pulse current up to 240 A, the current pulse duration of about 50 ns, and the pulse repetition rate up to 2 kHz. The duration and intensity of glow for standard CsI:Tl and Gd2O2S:Tb X-ray phosphors after their irradiation with X-ray flashes of about 50 ns duration are investigated. After X-ray radiation is converted into light, the signal is recorded using semiconductor detectors. We acquired several images of an object moving at a speed of about 20 m/s. A semiconductor detector with phosphor, which operates in the mode of continuous signal accumulation, is used. RESULTS: When using the pulsed X-ray source and phosphors with a short afterglow, the individual frames can be obtained at the pulse repetition rate of several kilohertz, and the detector does not contain the residual luminescence from the previous frame by the arrival of the next frame. CONCLUSIONS: The X-ray source shows good pulse-to-pulse reproducibility of X-rays, and can be used to capture objects in motion at a frame rate of several kHz. [ABSTRACT FROM AUTHOR]

PCMs are Non-Volatile Memories (NVMs) that store data using phase-change semiconductors, such as silicon-chalcogenide glass. In addition to increased integration density, PCMs have high durability and data transfer rates and consume less power during read/write operations. Compared with flash memory, PCM operates at much faster speeds and is close to the performance of DRAM. As a result, it is one of the most popular semiconductor memories which is used in various applications. However, PCM cells are limited to a certain number of write operations, and because of that, values cannot be changed when this limit is reached. Hence, PCMs do not last for a long time. The limited lifespan of PCM memory has led to considerable research in recent years. Several architectural levels and methods have been offered and examined to overcome this challenge. In this study, functional and practical techniques are identified and analyzed to extend the longevity of PCMs. These schemes can also be used to prolong the life of other NVM technologies since they share similar characteristics with PCMs. Furthermore, we will present some improvements to PCM performance to make it competitive with common NVMs. In conclusion, this survey will be helpful to both researchers who are considering starting PCM projects and those already proficient in PCM. [ABSTRACT FROM AUTHOR]

The multi‐level feature of GeTe/Sb2Te3 interfacial phase change memory was achieved by applying a designed voltage‐based pulse. It stably demonstrated five multi‐level states without interference for 90 cycles by varying the pulse width. GeTe/Sb2Te3 interfacial phase change memory demonstrated retention time of > 1.0 × 103 s, presenting the significantly low drift coefficient (ν) of < 0.009, indicating no resistivity drift due to the structure relaxation of glass. In addition, the reset energy consumption of GeTe/Sb2Te3 interfacial phase change memory was reduced by more than 85% compared to conventional Ge2Sb2Te5 phase change memory at each bottom electrode contact size. Multi‐level‐cell operation mechanism and gradual increase in conductance value of GeTe/Sb2Te3 interfacial phase change memory was explained by a partial resistance transition model where phase transition occurred partially in all layers. The result of the GeTe/Sb2Te3 interfacial phase change memory performance is expected to bring great advantages to the next‐generation storage class memory industry that requires low energy and high density. [ABSTRACT FROM AUTHOR]

Directionally solidified eutectics (DSEs) in Al 2 O 3 -based systems have been studied as high-temperature structural ceramics, also recently attracting attention as a phosphor screen for high-resolution radiation imaging. However, it is difficult to obtain uniform and thinly processed DSE in large areas. Here, we report a chemically deposited eutectic (CDE) of Lu 3 Al 5 O 12 (LuAG)–Al 2 O 3 using a laser-assisted chemical vapor deposition method. The Ce3+-doped LuAG lamella were epitaxially grew with an α-Al 2 O 3 matrix on an r-cut sapphire substrate. The Ce3+:LuAG–α-Al 2 O 3 CDE film exhibited green emissions due to the 5d–4f transitions of the Ce3+ center under UV light and α-/X-ray irradiations. The α-ray dose in the Ce3+:LuAG phase was estimated with Monte Carlo simulations to study a scintillation light yield of the CDE film. The X-ray radiograph of the semiconductor storage device was successfully obtained using a 15-μm-thick Ce3+:LuAG–α-Al 2 O 3 CDE film as an X-ray phosphor screen. • Chemically deposited eutectics in LuAG–Al 2 O 3 pseudobinary system. • α-Al 2 O 3 epitaxial growth with LuAG lamellar growth on sapphire. • TEM and EBSD reveals orientation distribution of LuAG with maintaining interface orientation to α-Al 2 O 3. • Monte Carlo simulation of α-ray dose explains the observed light yield of CDE. • X-ray radiograph using 15 μm-thick Ce3+:LuAG–Al 2 O 3 CDE film as X-ray phosphor screen. [ABSTRACT FROM AUTHOR]

[Display omitted] • Using a sequential technique involving an e-beam evaporator for vanadium metal and thermal post-oxidation, this research shows that stable VO 2 thin films with minimal interfacial mixing may be created. • The device has typical multi-level MIT properties with repeatable on/off switching behavior. • The device has excellent scalability on a wafer scale and has device-to-device stability. • The nanoscale IMT was probed by the conductive atomic force microscopy analysis. Vanadium dioxide (VO 2), as a representative metal-to-insulator transition (MIT) material, is of utmost interest for various device applications such as memory devices, memristors, Mott transistors, and temperature sensors due to its MIT temperature near room temperature. However, it is difficult to fabricate a stable VO 2 film, especially on Si wafer since its interfacial mixing alters the physicochemical properties of VO 2. This study demonstrates that stable VO 2 thin films with reduced interfacial mixing can be fabricated using a sequential process consisting of a vanadium metal e-beam evaporator and thermal post oxidation. The device fabricated with VO 2 shows distinctive multi-level MIT characteristics with bulk current–voltage curves with reproducible on/off switching behavior, which matches well with nanoscale transition probed by the conductive atomic force microscopy analysis. Our findings pave the way to produce highly stable VO 2 thin films as well as applications for integrated Si-based semiconductor devices such as memory devices, ultrafast switches, and others. [ABSTRACT FROM AUTHOR]

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HfxZr1−xO2 (HZO) thin films have excellent potential for application in various devices, including ferroelectric transistors and semiconductor memories. However, such applications are hindered by the low remanent polarization (Pr) and fatigue endurance of these films. To overcome these limitations, in this study, HZO thin films were fabricated via plasma-enhanced atomic layer deposition (PEALD), and the effects of the deposition and post-annealing temperatures on the density, crystallinity, and electrical properties of the thin films were analyzed. The thin films obtained via PEALD were characterized using cross-sectional transmission electron microscopy images and energy-dispersive spectroscopy analysis. An HZO thin film deposited at 180 °C exhibited the highest o-phase proportion as well as the highest density. By contrast, mixed secondary phases were observed in a thin film deposited at 280 °C. Furthermore, a post-annealing temperature of 600 °C yielded the highest thin film density, and the highest 2Pr value and fatigue endurance were obtained for the film deposited at 180 °C and post-annealed at 600 °C. In addition, we developed three different methods to further enhance the density of the films. Consequently, an enhanced maximum density and exceptional fatigue endurance of 2.5 × 107 cycles were obtained. [ABSTRACT FROM AUTHOR]