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Flip-flops are fundamental building block in designing the digital circuits. They contribute significant amount of power consumption in the digital systems. In the modern era of VLSI design, power consumption has become crucial factor. As the technology is scaled down below 65nm, leakage power contributes significantly to overall power consumption of digital circuits. Since, Flip-flop is a fundamental building block in designing digital systems, reducing the power consumption of Flip-flop is required to achieve low power consumption of digital systems. Recently single-phase clocking technique has been employed in designing FFs to achieve low power consumption. This technique reduces excess loading on the clock signal. In this article performance of recent single-phase clocked FFs is compared with the conventional transmission-gate Flip-flop. Also, drawbacks of these FFs are discussed. For the comparison of performance of single-phase-clocked FFs with conventional transmission-gate FF, all the simulations are performed at 45-nm predictive technology on Tanner EDA tool.