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Digital filter design optimization counts as one of the most challenging problems in circuit development. Furthermore, the bit-width allocation has a crucial impact on the efficiency and accuracy of fixed-point digital filters. The conventional implementation procedure involves studying the bit-width allocation problem after determining the filter coefficients. This sequential procedure leads frequently to an excessive bit-width allocation, hence an extra implementation cost. The main contribution of this paper is to propose a new implementation procedure based on the simultaneous handling of both design issues and the bit-width optimization for the infinite impulse response filter. In this study, the problem is formalized by a multi-objective programming technique using the non-dominated sorting genetic algorithm II. The joint consideration of the two problems offers a better trade-off between design and bit-width allocation. The output of our approach is compared to the results of existing algorithms. Simulation results show that the multi-objective method significantly reduces the implementation cost while ensuring filter stability and an acceptable mean square error (MSE) compared to the existing algorithms. [ABSTRACT FROM AUTHOR]

This paper addresses the precision analysis of filters in the parallel form framework. The precision analysis consists of determining suitable fractional bit-widths to set a tradeoff between resource consumption and computational accuracy. Although the stability of the parallel form is relatively better controlled than the related direct form, its bit-width optimization did not receive much consideration in the literature, despite its significant contribution to the optimization of the filter's physical implementation. To carry out the needed bit-width optimization, we present two heuristics based on the Estimation of Distribution Algorithm, which falls within the category of probabilistic model-building genetic algorithm. The performance of the proposed approach is discussed, and compared to chosen benchmarks, the results show that our hardware implementations reduce the cost of the resulted circuits up to 37 % . [ABSTRACT FROM AUTHOR]