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In bridgeless power factor correction converters and inverters, GaN high-electron-mobility transistors (HEMTs) operate in both forward and reverse conduction modes, which may feature different dynamic on-resistance (RON) behaviors. Despite the extensive study of dynamic RON under forward conduction, dynamic RON under reverse conduction still demands comprehensive evaluation. In this letter, the dynamic RON of two commercial p-GaN gate HEMTs with different technologies under forward/reverse conduction and hard/soft switching is characterized using the custom-designed multigroup double pulse test system, which nearly eliminates the accumulated self-heating effect in the device. First, the test was conducted at off-state bias voltage = 400 V, IDS = 70% IDS(max). For the Schottky-type p-GaN gate HEMTs, the dynamic RON in reverse conduction is found to be more than 3%–5% higher compared to the forward conduction. However, for the hybrid-drain-embedded gate injection transistor, operating in reverse conduction mode leads to a slighter dynamic RON degradation effect, with a reduction of approximately 10% compared to the forward conduction. Next, IDS was modulated to evaluate its impact on dynamic RON. For both devices, during reverse conduction it was observed that the dynamic RON initially decreases and subsequently increases with the IDS increase.

GaN-based tunnel-oxide-free charge trapping memory (CTM) that exploits deep-level interface states and large junction barriers for charge storage has been demonstrated, exhibiting high speed, high endurance, and long retention time. To enhance the data storage capacity, high-density deep-level states at the charge-trapping interface are required. In this letter, we demonstrate the multi-state operation of a GaN-based CTM with an AlN interfacial layer prepared by plasma-enhanced atomic layer deposition (PEALD). The thin PEALD-AlN interfacial layer, positioned between the Al2O3 and the p-GaN channel, increases the memory window (MW) due to the formation of high-density interface states. Post-metallization annealing performed in N2 ambient at $420~^{\circ }$ C improves charge retention, with an extrapolated room-temperature retention time exceeding $10^{{9}}$ s. Based on these, the GaN-based CTM achieves a large MW over 5 V, 2-bit/cell operation, and long-term analog-state storage.

The human-body-model (HBM) electrostatic discharge (ESD) robustness can be directly evaluated through the ESD simulator designed for product qualification or indirectly by the transmission line pulse (TLP) I–V system. Although the TLP test can be used to estimate drain-to-source HBM ESD robustness of Si mosfets, it causes misleading estimation for GaN HEMTs. To understand this miscorrelation, the behaviors of 100-V Schottky-type p-GaN gate HEMTs and Si mosfets under HBM ESD tests are characterized and compared in this work, especially the rise time (tR) of terminal voltages in the devices. In drain-to-source ESD of the Si mosfet and gate-side ESD of the GaN HEMT, the high leakage current and the device voltage clamping result in short tR (∼10 ns) and strong ESD robustness. In most other HBM ESD tests, the two devices behave like variable capacitors with long tR (>100 ns) due to the insignificant leakage current. Moreover, the breakdown voltage of GaN HEMTs is dependent on the voltage stress time. Since the appropriate HBM–TLP correlation is based on the assumption of short tR and weak time dependence of device breakdown, the TLP I–V test is not suitable for HBM ESD robustness evaluation of GaN HEMTs. Instead, a more accurate and simpler estimation of HBM ESD robustness can be realized by a versatile pulse I–V system with adjustable tR.

The design of gate drivers for silicon carbide (SiC) power mosfets needs to address various adverse effects induced by the parasitic inductance in the gate loop, such as false turn-on, gate overstress, and reduced switching speed. In this work, a single-polarity gate driver design featuring a low-voltage (LV) gallium nitride (GaN) high-electron-mobility transistor (HEMT) for Miller clamping is presented. The lateral LV GaN HEMT can switch at a much higher speed than that of the SiC mosfet, so that the proposed gate driver can well suppress false turn-on with a user-friendly off-state gate voltage of 0 V. Meanwhile, the reverse-conduction characteristics of the LV GaN HEMT allow the clamping of negative voltage spikes to protect the SiC mosfet against gate overstress, which is shown to be detrimental to the gate reliability. In addition, the LV GaN HEMT can accelerate the turn-off process and suppress the gate-loop oscillation, thereby further reducing the switching loss, as verified by experiment results.

The planar nature of the GaN heterojunction devices provides extended dimensions for implementing monolithic power integrated circuits. This article presents a comprehensive review of the advancements in GaN power integration. Basic building blocks in a power integration platform based on p-GaN gate HEMT technology are discussed, including high- and low-voltage transistors, lateral field-effect rectifiers, resistors, and capacitors. Exemplary designs of monolithic gate driving circuit and detection/protection circuits based on this platform are demonstrated. Technologies to address other challenges, including the lack of mature complementary logic (CL) and the substrate-induced crosstalk effect, are also demonstrated. More forward-looking development of power integration based on wide bandgap semiconductors is also presented in a hybrid GaN/SiC field-effect transistor that is expected to harness the complementary merits of GaN and SiC, and ON-chip GaN-based nonvolatile memory device that could provide versatile intelligence.

The conventional ${p}$ -GaN in Schottky-type ${p}$ -GaN gate HEMTs is converted into an insulator-like ${p}$ -GaN, i.e., fully depleted ${p}$ -GaN in the reverse-biased Schottky junction under forward gate bias ( ${V}_{\text {GS}}$ ), by inadequate activation of Mg. Consequently, the gate current ( ${I}_{\text {G}}$ ) is reduced by 3–5 orders of magnitude at ${V}_{\text {GS}}$ of 7-V over a temperature range of 25 °C–150 °C, compared with devices adopting conventional adequate activation. The fully depleted ${p}$ -GaN converts the current-balance-based forward ${V}_{\text {GS}}$ division in the conventional partially depleted ${p}$ -GaN gate stack, into thickness-based voltage division in ${p}$ -GaN and AlGaN between gate and channel, which is like that in a MIS (metal-insulator-semiconductor) gate. As a result, the hole current through the Schottky junction is significantly reduced while the electron spillover current starts to dominate at high forward ${V}_{\text {GS}}$ . Besides, hot carriers are excluded from the forward gate breakdown mechanism.

We characterize and evaluate the RF linearity of an enhancement-mode ${p}$ -GaN gate high-electron- mobility-transistor (HEMT) on a 200-mm high-resistivity-silicon substrate. Nearly flat transconductance and its small derivatives, together with relatively uniform small-signal parameters within the operating range, predict good linearity performances of the scaled-down device. With a two-tone technique, the device shows the peak output third-order intercept point (OIP3) of 38.9-dBm at 5 GHz for a 300- $\mu \text{m}$ -gate-width device and the corresponding linearity figure of merit OIP3/ ${P}_{\text {DC}}$ of 14.1-dB. A low power ratio of the third-order intermodulation to the fundamental carrier output (IM3/C) smaller than −50-dBc is also obtained at 8-dB backoff from the single-tone P1dB compression point.