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In this work, an in-depth static and low frequency noise characterization of nanosheet FETs, consisting of two vertically stacked silicon channels per device, is performed. A comparison of the performances from n- versus p-channel FETs operated at 300 K and 78 K, in terms of static and low frequency noise parameters variability, is also discussed. The main electrical parameters are estimated from the I-V characteristics using access resistance robust methodologies. An additional criterion demonstrating that the extracted parameters are not influenced by the second mobility attenuation factor is proposed. The low frequency noise studies prove that the dominant flicker noise mechanism is linked to correlated carrier number and mobility fluctuations, with additional access resistances noise contribution in very strong inversion. The importance of the considered total flicker noise model on the estimation of the Coulomb scattering coefficient is highlighted.

In this work, two types of gate-all-around (GAA) vertically stacked silicon nanosheet (NS) FETs are investigated, the main difference being the vertical distance between the stacked NSs. Principal electrical parameters are estimated at room and liquid nitrogen temperatures using a refined Y -function methodology, the main advantage being that no extra iterative steps are necessary. The results are confirmed using other derivative dc parameter estimation methodologies. Low-frequency noise measurements evidence variability of the flat-band voltage noise and correlation between the noise level and the low field mobility. The dominant flicker noise mechanism is related to the correlated mobility and carrier number fluctuation mechanism with access resistance noise contribution in very strong inversion. The impact of the access resistance on the estimation of the Coulomb scattering coefficient is evidenced.

The low-frequency (LF) noise characterization of Si0.7Ge0.3 pFinFETs and transistors’ performance were analyzed for different NH3 post deposition annealing (PDA) temperatures. The flicker noise of these pFinFETs is dominated by carrier number fluctuations at low and intermediate drain currents. At high gate overdrive, the voltage noise Svg increases dramatically and the effect of the access resistance cannot be ignored. By analyzing the input-referred voltage noise power spectral density(PSD) at flat band voltage ( Svgfb ), we will demonstrate that nitridation of the high- κ layer at 650 °C yields the best quality gate-stack and also results in the highest mobility. While NH3 PDA temperature above 650 °C may introduce more hydrogen at the oxide layer and at the interface, hydrogen can induce hole traps and interface traps that degrade the quality of the gate-stack and reduce the mobility.

We report on vertically stacked nanosheet (NS) FET devices as the most promising candidates to replace finFETs, discussing some of their key features and potential extension and/or alternative options to help preserve the power, performance, area, and cost (PPAC) logic roadmap for advanced sub-5nm technology nodes, being also attractive for cold computing. In addition, given the increased complexity and cost in back-end-of-line processing, to take full advantage of the scaling performance benefits at transistor level it has also become ever more pressing to address signal and power wiring bottlenecks. The concept of moving power delivery to the wafer’s backside has been gaining traction and we will thus also explore it in this work by combining logic and 3D technologies and assess its feasibility by evaluating the impact of 3D processing on device characteristics.

Here, it has been verified through numerical simulations calibrated to experimental data the changes that the insertion of a germanium layer can bring to the electrical power generation of a silicon solar cell. The studied device is a lateral PIN photodiode embedded in a wafer with SOI (Silicon-On-Insulator) technology as part of a CMOS (Complementary Metal Oxide Semiconductor) circuit. The insertion of a germanium layer on top or below a silicon PIN diode has been considered. Results showed that different semiconductor characteristics (bandgap, mobility, and absorption coefficients) result in a general improvement in the solar cell performance, therefore allowing a better understanding of the phenomena that occur in the photogeneration of a cell with a heterojunction between germanium and silicon.

Made available in DSpace on 2022-04-28T19:51:21Z (GMT). No. of bitstreams: 0 Previous issue date: 2022-05-01 In this work the gate-all-around nanosheet transistor is analyzed at high temperatures, from analog point of view. At first, the gate-all-around nanosheet (NS) behavior is compared with reported omega-gate nanowire (NW) transistors, at room temperature. It is worth noting that the nanosheets devices present a stronger electrostatic coupling between gate and channel (lower short channel effect -SCE), and higher intrinsic voltage gain, AV (better Early voltage) when compared with NW devices (60 dB for NS and 55 db for NW, with L = 200 nm). Therefore, the second part of this work focuses on the analog study only for NS transistors (with different metal gate stacks), presenting the trade-off between transistor efficiency and unit gain frequency, fT from room temperature to 200 °C. The obtained results are very promising for both gate stack transistors, where values of transistor efficiency about 37 V−1 (T = 25 °C and L = 200 nm) and fT about 260 GHz (T = 25 °C and L = 28 nm) are obtained. The optimal application point was obtained at the transition from moderate to strong inversion. LSI/PSI/USP University of Sao Paulo imec UNESP Sao Paulo State University UNESP Sao Paulo State University

Made available in DSpace on 2022-04-28T19:49:41Z (GMT). No. of bitstreams: 0 Previous issue date: 2022-03-01 In this work, a Gate-All-Around Nanosheet transistor (GAA-NSH) is used to design an operational transconductance amplifier (OTA) operating from room temperature to 200 °C. A simulation model for the transistor was created using Verilog A language including a lookup table (LUT) with current response and capacitance data obtained from measurement of fabricated devices. Two OTA designs were made, for supply voltages (VDD) of 2.1 V and 1.5 V. The first design was analyzed at room temperature (25 °C) with different bias points that defined the transistors efficiency (gm/ID) of the first stage input differential pair and current mirror load. A comparison with other OTA projects using FinFET and Tunnel FET (TFET) devices was performed considering similar gm/ID for all designs. The GAA-NSH design presents a larger voltage gain than the FinFET design (71.8 dB vs. 67.6 dB), while consuming less power (544.5uW vs. 1.41mW) and utilizing smaller devices and an overall smaller area footprint. Improvements are a consequence of the superior gate electrostatic coupling of the GAA-NSH transistors that can be seen through the improved transconductance and output conductance values. Compared with the TFET device, the GAA-NSH presents a tradeoff between Bandwidth and power consumption. Finally, the second OTA designed is analyzed from room temperature to 200 °C, and a decrease of the voltage gain and GBW was observed due to the mobility degradation at high temperature. LSI/PSI/USP University of Sao Paulo ECE University of Toronto imec UNESP Sao Paulo State University UNESP Sao Paulo State University

In this work, the impact of the channel doping density on the low-frequency noise of silicon Gate-All-Around (GAA) Vertical Nanowire (VNW) pMOSFETs on Silicon-on-Insulator (SOI) substrates will be described and discussed. It is demonstrated that the dominant fluctuation mechanism of the 1/f noise in the subthreshold regime changes from number (Δn) to mobility (Δμ) fluctuations with increasing p-type doping density of the silicon nanowires. At the same time, the lowest input-referred voltage noise Power Spectral Density is observed for an intermediate boron concentration in the nanowire of 5 × 10^18 cm^(-3).

Since the early days of the semiconductor industry, defect control has been key to the successful development of devices and circuits. It requires a thorough understanding of their formation and the impact on the electrical material parameters. This has only been possible by the invention of powerful structural, chemical and electrical characterization tools, with the device itself perhaps as the most sensitive probe. This evolution was paralleled by the development of ab initio calculation methods, based on Density Functional Theory and more recently, also TCAD tools allowing more and more refined modelling of the impact of defects on the electrical characteristics of devices. The implementation of other materials than Si and SiO2 in CMOS through the hetero-epitaxial growth on a silicon substrate for example, has renewed the interest in defect engineering during the last two decades, leading to single-defect analysis methods like Random Telegraph Noise (RTN) [1] or novel growth schemes like Aspect Ratio Trapping (ART) [2] for the removal of extended defects from the device active regions. In this presentation, some state-of-the-art analysis techniques will be highlighted, including Deep Level Transient Spectroscopy (DLTS) [3], Generation-Recombination (GR) noise and RTN spectroscopy [1,4] and p-n diode lifetime analysis [5]. These methods will be applied to several case studies. As shown in Fig. 1, threading extended defects impact the recombination lifetime of lowly-doped n-type In0.47Ga0.53As starting from a density of a few 107 cm-2. Likewise, it will be demonstrated that the GR noise observed in GaN-on-Si MOSHEMTs (Fig. 2) most likely originates from threading dislocations [6]. It is concluded that when hetero-epitaxial layers can be grown with a sufficiently low defect density, their impact will be more on the variability of the electrical parameters rather than on the effective values. In addition, the position of the defect with respect to strategic nodes like a p-n junction or depletion region largely determines its electrical impact, as has been validated by TCAD simulations. References [1] E. Simoen and C. Claeys, “Random Telegraph Signals in Semiconductor Devices”, The Institute of Physics, Bristol, UK (2016). [2] J. Z. Li et al., Appl. Phys. Lett., 91, p. 021114 (2007). [3] E. Simoen, J. Lauwaert and H. Vrielinck, Semiconductors and Semimetals, Eds. L. Romano, V. Privitera and C. Jagadish, 91, pp. 205-250, Elsevier 2015. [4] D. Boudier et al., Solid-St. Electron., 128, pp. 102-108 (2017). [5] Po-Chun (Brent) Hsu et al., J. Phys. D: Appl. Phys., 52, p. 485102 (2019). [6] K. Takakura et al., IEEE Trans. Electron Devices, 67, pp. 3062-3068 (2020). Figure 1

CMOS scaling has been the backbone of the overall logic roadmap for decades, but it is reaching its physical limits while also imposing ever more constraining design restrictions. This has triggered a critical need for new device architectures and integration concepts to be able to continue delivering profitable node-to-node scaling gains and to help preserve the industry’s power-performance-area-cost metrics. From the transistor’s perspective, vertically stacked lateral nanosheet (NS) FETs, with a gate-all-around (GAA) configuration, are widely regarded as the most promising and mature option to replace finFETs. Reduced gate lengths should be feasible thanks to their improved electrostatics, thus allowing further scaling of the contacted-gate-pitch and of the cell height via a reduced number of metal tracks. Other key characteristics include high design flexibility, with various NS widths possible on a given wafer, and larger drivability per layout footprint by increasing the number of vertically stacked NS per device and/or using wider NS [1,2] (Fig.1). An extension of this technology could in principle be envisioned by strongly reducing the p-n separation in the so-called forksheet configuration [3]. Beyond that, the concept of stacking devices with different polarity on top of each other is also being looked at [4,5]. Other future technology candidates include FETs with vertical transport [6] and non-silicon channels [7]. Each new architecture will have its own specific challenges such as the internal routeability for stacked structures in functional logic blocks (e.g., standard cell or SRAM) but, in general, many elements can be shared by the various branches of the NS family of devices. Overall, a careful balance between drive strength and capacitance is required in NS FETs engineering. In particular, the presence of dielectric inner spacers in-between vertically stacked nanosheets is a critical element, also as it leads to a different growth regime for the source/drain (S/D) epi as compared to the situation in finFETs [8]. This is an important differentiator as channel strain induced by S/D has been traditionally used to boost device performance. The feasibility of continuing using process-induced stress techniques for mobility enhancement is in fact a key challenge for several new architectures, namely for the top device in stacked structures or when S/D are placed in different vertical levels. Moreover, faced with power scaling stagnation, cold computing is also becoming an attractive option to consider for enabling high performance boosting in an energy efficient way. Our results confirm improved DC properties for NS FETs (e.g., subthreshold swing (SS), mobility), with similar mechanisms responsible for their noise behavior at room and low temperatures (300K (RT), 78K) [9]. In addition to the need for the introduction of new transistor technologies, given the increased complexity and cost in back-end-of-line processing, it has also become ever more pressing to address both wiring and power delivery network (PDN) bottlenecks to take full advantage of the scaling performance benefits at transistor level. The concept of moving the PDN to the wafer’s backside (BS) such that it can alleviate routing congestion on its frontside (FS) has been recently gaining traction [10,11]. This is illustrated in Fig.2 wherein, by combining logic and 3D technologies, both wafer sides are used. In our work, after frontside processing, device and carrier wafers are bonded at RT, including a 523K post-bond anneal. Extreme wafer thinning is then implemented prior to nano-through-silicon-vias (n-TSV) definition (landing on the metal-1 level (M1) in the frontside) and backside metallization. Evaluating the impact on scaled transistors from BS processing, our results show similar p/n threshold voltages (VTs) can be obtained with an extra sinter at the end of fabrication. Inclusion of an additional high-pressure H2-anneal prior to the final sinter is also seen to help lower the SS values for pmos without significant IOFF effect. Reliability-wise, constant ramped voltage stress measurements also show no BTI degradation for p/nmos, with additional indication of potential benefits by the final anneal(s) treatment selection. These findings are further corroborated by LF-noise analysis. References [1] N. Loubet et al., VLSI Tech. Dig., 2017, p.230. [2] A. Veloso et al., SSDM Tech. Dig., 2019, p.559. [3] P. Weckx et al., IEDM Tech. Dig., 2019, p.871. [4] W. Rachmady et al., IEDM Tech. Dig., 2019, p.697. [5] C.-Y. Huang et al., IEDM Tech. Dig., 2020, p.425. [6] A. Veloso et al., IEDM Tech. Dig., 2019, p.230. [7] P.-C. Shen et al., Nature, 2021, Vol.593, p.211. [8] G. Eneman et al., ECS Trans., 2020, Vol.98(5), p.253. [9] B. Cretu et al., EuroSOI-ULIS Tech. Dig., 2021. [10] A. Veloso et al., VLSI Tech. Dig., 2021, TFS2-6. [11] https://www.intel.com/content/www/us/en/events/accelerated.html. Figure 1

Herein, the carrier lifetime in approximately 5x10^16 cm^(-3) n-doped In(x)Ga(1-x)As layers is studied by diode current–voltage analysis and by time-resolved photoluminescence. Two sets of hetero-epitaxial layers are grown on semi-insulating InP or GaAs substrates. The first set corresponds with a constant In content p + n stack, while the second set has a fixed x = 0.53 for the n-layer, while containing various extended defect densities by using a strain relaxed buffer with different x. This results in threading dislocation densities (TDDs) between approximately 10^5 cm^(-2) and a few 10^9 cm^(-2). It is shown that the overall trend of the recombination lifetime versus TDD can be described by a first-order model considering a finite recombination lifetime value inside a dislocation core of 1 nm. For the generation lifetime, a strong electric-field enhancement factor is found. Also, the residual strain in the n-layer has an impact. Overall, the safe limit for TDD depends on the type of application and on the operation conditions (reverse diode bias).