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Metal oxide thin‐film transistors (TFTs) offer remarkable opportunities for applications in emerging transparent and flexible microelectronics. Unfortunately, their performance is hindered by limitations associated with parasitic effects, such as parasitic electrode overlap capacitances and high contact resistance, which can severely limit their dynamic behavior. Here, an innovative method is reported to fabricate coplanar self‐aligned‐gate (SAG) indium‐gallium‐zinc‐oxide (IGZO) transistors with engineered source/drain contacts. The manufacturing process starts with the deposition and patterning of a gate electrode/dielectric stack and its functionalization with an organic self‐assembled monolayer (SAM) as the surface energy modifier. A second gold (Au) electrode is subsequently deposited over the gate electrode stack. The overlapping region between the two electrodes is removed via self‐delamination under mild sonication, forming perfectly aligned coplanar Au‐Gate‐Au electrodes. Device fabrication is completed with the spin coating of the IGZO precursor, followed by rapid photonic curing. Replacing the gold source/drain contact with bimetallic electrodes such as Au/In and Au/ITO enables a reduction in contact resistance and improves the transistor performance remarkably without increasing manufacturing complexity. The method is highly scalable, robust, and applicable to other semiconductor materials. [ABSTRACT FROM AUTHOR]

We demonstrate the compensation of device‐to‐device variation in threshold voltage using programmable ferroelectric indium‐gallium‐zinc‐oxide thin‐film transistors. Furthermore, degradationinduced threshold voltage shift can be mitigated by programming, setting the characteristics back to their pristine state. This can be a promising alternative for the replacement of complex VT compensation circuits in display applications. [ABSTRACT FROM AUTHOR]

Brain‐inspired neuromorphic computing has drawn significant attraction as a promising technology beyond von Neumann architecture by using the parallel structure of synapses and neurons. Various artificial synapse configurations and materials have been proposed to emulate synaptic behaviors for human brain functions such as memorizing, learning, and visual processing. Especially, the memory type indium‐gallium‐zinc‐oxide (IGZO) synaptic transistor adopting a charge trapping layer (CTL) has the advantages of high stability and a low leakage current of the IGZO channel. However, the CTL material should be carefully selected and optimized to overcome the low de‐trapping efficiency, resulting from difficulty in inducing holes in the IGZO channel. In this paper, IGZO is adopted as a CTL and found out that making it degenerated is crucial to improving de‐trapping efficiency. The degenerate CTL, where electrons remain as free electrons, induces Fowler‐Nordheim tunneling by increasing the electric field across the tunneling layer. As a result, the synaptic transistor represents a high linearity of potentiation (αp: −0.03) and depression (αd: −0.47) with 64 conductance levels, which enables the spiking neural network simulation to achieve high accuracy of 98.08%. These experimental results indicate that the synapse transistor can be one of the promising candidates for neuromorphic applications. [ABSTRACT FROM AUTHOR]

Abstract Brain‐inspired neuromorphic computing has drawn significant attraction as a promising technology beyond von Neumann architecture by using the parallel structure of synapses and neurons. Various artificial synapse configurations and materials have been proposed to emulate synaptic behaviors for human brain functions such as memorizing, learning, and visual processing. Especially, the memory type indium‐gallium‐zinc‐oxide (IGZO) synaptic transistor adopting a charge trapping layer (CTL) has the advantages of high stability and a low leakage current of the IGZO channel. However, the CTL material should be carefully selected and optimized to overcome the low de‐trapping efficiency, resulting from difficulty in inducing holes in the IGZO channel. In this paper, IGZO is adopted as a CTL and found out that making it degenerated is crucial to improving de‐trapping efficiency. The degenerate CTL, where electrons remain as free electrons, induces Fowler‐Nordheim tunneling by increasing the electric field across the tunneling layer. As a result, the synaptic transistor represents a high linearity of potentiation (αp: −0.03) and depression (αd: −0.47) with 64 conductance levels, which enables the spiking neural network simulation to achieve high accuracy of 98.08%. These experimental results indicate that the synapse transistor can be one of the promising candidates for neuromorphic applications.

Atomic layer deposition (ALD) has been studied extensively to employ oxide semiconductor thin film transistor (TFT) including both active layer and gate insulator (GI). Herein, we developed an ALD sandwich structure, which deposits both semiconductor and GI by ALD. In contrast to the previous results using sputter In-Ga-Zn-O (IGZO), ALD sandwich structure IGZO TFT exhibited severe deterioration in its electrical performance when the Al2O3 was adopted for both buffer layer and GI application. Through measurement of hydrogen permeability of ALD insulators and secondary ion mass spectroscopy of each sandwich structure after annealing, we found a hydrogen accumulation effect between Al2O3 and ALD IGZO interface layer, which caused deterioration of electrical performance. In contrast, TFTs with ALD SiO2, which has proper hydrogen diffusivity, chosen as the buffer and GI had favorable electric properties of 28.17 cm2/ $\text{V}\cdot \text{s}$ , 0.20 V/dec, 0.96, and 0.12 V for the mobility, ${V}_{\text {th}}$ , subthreshold swing (SS), and hysteresis. In this regard, an optimized GI structure via the ALD SiO2 and Al2O3 in situ process based on excellent interface formation with the semiconductor and hydrogen barrier performance, respectively, was developed. This functional GI structure consisting of SiO2 and Al2O3 exhibited excellent TFT characteristics (27.52 cm2/ $\text{V}\cdot \text{s}$ , 0.24 V/dec, and 1.07 V for the mobility, SS, and ${V}_{\text {th}}$ , respectively) with improved stability even after hydrogen annealing, which was used to examine the resistance to external hydrogen, showing a threshold voltage shift of −0.15 V and a SS shift of 0.01 V/dec. [ABSTRACT FROM AUTHOR]

Metal-oxide high- k dielectric films have received considerable attention in lowering the driving voltage and power consumption in semiconductor devices. Here, we demonstrate sub-volt operating metal-oxide thin-film transistors (TFTs) using solution-processed high- k gadolinium-doped hafnium oxide (HGO) dielectric films. Particularly, the HGO dielectric films were fabricated using a solution combustion synthesis (SCS) method using acetylacetone and 1,1,1-trifluoroacetylacetone as cofuels. The HGO dielectric films exhibited low leakage current of 2.7 × 10−6 A/cm2 at 1 MV/cm and dielectric constant of ∼17. It was found that the Gd doping had a significant impact on improving the leakage current characteristics compared to the undoped HfO 2 films (leakage current of ∼10−2 A/cm2 at 1 MV/cm). By employing the high- k HGO gate dielectric layer, we demonstrated 0.5 V-operating indium-gallium-zinc-oxide TFTs exhibiting field-effect mobility of 3.55 cm2/Vs, on/off ratio of 5.9 × 105, and subthreshold slope of 75 mV/decade. We investigated the effects of cofuel concentration on the film morphology and dielectric properties of HGO films to determine the optimal cofuel concentration for SCS. Furthermore, X-ray photoelectron spectroscopy was performed to reveal the role of Gd doping in improving the dielectric properties in correlation with the oxygen vacancy formation. Based on these results, we claim that the high- k HGO film fabricated through the SCS route can be a promising candidate for realizing sub-volt operating TFTs for low-power consumption. [Display omitted] • High- k Gd-doped HfO 2 dielectric films are fabricated using a solution process. • Influences of Gd doping and cofuel concentrations on the dielectric properties are investigated. • The effects of annealing time on oxygen binding states, crystalline structure, and dielectric properties are investigated. • Sub-volt IGZO TFTs are demonstrated using Gd-doped HfO 2 gate dielectric layer. [ABSTRACT FROM AUTHOR]

Improving reliability of low-temperature polycrystalline silicon (LTPS) and amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistors (TFTs), components of low-temperature polycrystalline silicon and oxide (LTPO), is crucial for fabricating high-performance and high-stability LTPS and oxide semiconductor-based electronics and display products. However, improving the reliability of these TFTs simultaneously in a uniform and effective manner within a coplanar structure is challenging. In this work, high-pressure H 2 O post-annealing (H 2 O HPPA) as a post-treatment for LTPS and a-IGZO TFTs within a coplanar structure are proposed to improve the uniformity and stability of the electrical characteristics simultaneously. It was demonstrated that oxygen and hydrogen in the HPPA-passivated defect state at the channel/gate dielectric layer interfaces and bulk gate dielectric layers of LTPS and a-IGZO TFTs considerably improve the uniformity and stability of the electrical performance and morphologies of the interfaces. Thus, the distribution of electrical characteristics (mobility, threshold voltage, and subthreshold swing) in LTPS and a-IGZO TFTs was reduced by more than 2-fold, and the trap charge densities at their interfaces and bulk gate dielectric layers were reduced by approximately 1.6-fold. Furthermore, the threshold voltage shift was decreased in both LTPS and a-IGZO-TFTs fabricated with H 2 O HPPA under negative and positive bias temperature stresses, respectively. The proposed H 2 O HPPA method can effectively facilitate the industry-level application of LTPS and oxide semiconductor-based electronics and display electronics. • The effect of LTPS and a-IGZO thin film transistors fabricated by high-pressure H 2 O post-annealing were analyzed. • O 2 and H 2 induced in H 2 O HPPA suppress defects in dielectric/channel interface and dielectric bulk of LTPS and a-IGZO TFT. • Both LTPS and a-IGZO TFTs treated by H 2 O HPPA significantly improved uniformity and reliability of electrical performance. [ABSTRACT FROM AUTHOR]

We propose a compact multilayer thin film color pixel and a method for efficient transmissive color in the visible regime. When the angle of incidence (AOI) varies between 0° and 60°, there is almost no change of the transmitted color. Meanwhile, additional dielectric layers at the top and bottom of the hybrid structure work as anti-reflection (AR) layers, which greatly improve the transmission efficiency. The performance can be switched by adjusting the thickness of the film, as well as controlling the charge carrier concentration in a doped indium-gallium-zinc-oxide (IGZO). Besides their simple, large scale compatible, and electron beam lithography (EBL) free fabrication route, the designed structure provides relatively high efficiency, high color purity, and low crosstalk, which may provide some new insights for structural color applications. [ABSTRACT FROM AUTHOR]

Indium–gallium–zinc oxide (IGZO) thin films were prepared in a N 2 environment by varying the annealing pressure and then tested for NO 2 gas detection. These thin films, whose average thickness ranged between 5 and 100 nm, were deposited via the sputtering on alumina substrates equipped with interdigitated Au electrodes using an IGZO polycrystalline target (ZnO: Ga 2 O 3 :In 2 O 3 = 1:1:1 mol%). The effects of annealing pressure and environment were investigated. A superior sensor response (S) was observed when increasing the annealing pressure; the prepared IGZO thin film showed an S of –800 at an operating temperature of 250 °C for 25 ppm NO 2 gas. The recovery time decreased with increasing the annealing temperature. The sensor annealed at 400 °C at 3 atm showed superior selectivity to various gases and longtime stability of 60 days was attained. The role of the oxygen vacancies in the sensor performance was also investigated. • High pressure annealing (HPA) effect on Indium-Gallium-Zinc-Oxide (IGZO) films are demonstrated for high response to NO 2 gas. • Sensor response (S = R gas /R air) of S – 800 was achieved for 25 ppm concentration of NO 2 gas. • Modulation of Oxygen Vacancy (O vac) was observed by High pressure annealing on IGZO film. • IGZO Sensor show superior stability and selectivity. [ABSTRACT FROM AUTHOR]

[Display omitted] • We use self-assembled monolayers (SAMs) to reduce gate leakage of top-gated IGZO TFT. • We engineer the IGZO/dielectric interface by dipolar, silane-anchored SAMs. • We characterize SAMs in detail by a combination of several complementary techniques. • The SAMs providing a favorable built-in electric field to reduce the leakage current. • The results correlate well with electron accepting or donating characters of SAMs. Top gate (TG) thin film transistors (TFTs) featuring amorphous metal oxide semiconductors (a -MOS), such as indium-gallium-zinc-oxide (IGZO), bear a great potential for large-area flexible and transparent electronics. The fabrication costs of these devices can be noticeably reduced by introduction of solution processes instead of standard fabrication routes involving vacuum deposition and complicate photolithography. However, solution-processed TG a -MOS TFT often causes considerable gate leakage in comparison with vacuum-processed device. In this context, we present a simple and straightforward approach to reduce the gate leakage of IGZO-based TG TFTs, which predominantly involves solution-based procedures. We engineer the IGZO/insulator interface by dipolar, silane-anchored self-assembled monolayers (SAMs) providing a favorable built-in electric field to reduce the leakage current in TFTs. The parameter correlates well with the direction and value of the molecular dipole moment defined by either electron accepting or electron donating character of the terminal tail group. These SAMs, prepared by spin-coating procedure, were characterized in detail by a combination of several complementary experimental techniques, providing also a useful background information for the device experiments. [ABSTRACT FROM AUTHOR]