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Your search keyword '"Jang, Won Ho"' showing total 10 results
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10 results on '"Jang, Won Ho"'

2. 47‐1: Invited Paper: A 6Gbps Intra‐Panel Interface with Video Image Compression for Next Generation Displays.

Author

Jang, Won-Ho, Ryu, Kyungho, Lim, Jung-Pil, Jung, Jicheol, Han, Junho, Han, Mangi, Kwon, Yongil, Lim, Hyun-Wook, and Lee, Jae-Youl

Subjects
IMAGE compression, VIDEO compression, VOLTAGE, CALIBRATION, BANDWIDTHS
Abstract

This paper proposes a 6Gbps receiver for 8K 240Hz OLED display. In the proposed receiver, video image compression is presented to double the effective data bandwidth. In addition, it proposes dual path CTLE offset voltage calibration and CTLE adaptation with eye margin tester to implement 6Gbps receiver. The prototype IC is implemented in a 0.18μm HVCMOS process and is evaluated as an 8K 65‐inch panel. [ABSTRACT FROM AUTHOR]

Published
2024
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4. 47‐1: Invited Paper:A 6Gbps Intra‐Panel Interface with Video Image Compression for Next Generation Displays

Author

Jang, Won-Ho, Ryu, Kyungho, Lim, Jung-Pil, Jung, Jicheol, Han, Junho, Han, Mangi, Kwon, Yongil, Lim, Hyun-Wook, and Lee, Jae-Youl

Abstract

This paper proposes a 6Gbps receiver for 8K 240Hz OLED display. In the proposed receiver, video image compression is presented to double the effective data bandwidth. In addition, it proposes dual path CTLE offset voltage calibration and CTLE adaptation with eye margin tester to implement 6Gbps receiver. The prototype IC is implemented in a 0.18μm HVCMOS process and is evaluated as an 8K 65‐inch panel.

Published
2024
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10. 23‐3: Distinguished Paper:A Clock Embedded Intra‐panel Interface with 1.96% Data Overhead for Beyond 8K Displays

Author

Park, Yong-Yun, Jang, Won-Ho, Kim, Kyoung-Ho, Ryu, Kyungho, Lim, Jung-Pil, Kwon, Yongil, Lim, Hyun-Wook, and Lee, Jae-Youl

Abstract

This paper proposes a 6Gb/s receiver for 8K displays and beyond. In the proposed receiver, a novel channel coding with 1.96% overhead is presented to guarantee minimum run‐length in the clock embedded interface. It can also reduce bandwidth for effective data transmission compared to 9b/10b coding that requires 11.11% overhead. Furthermore, we present an on‐chip eye margin tester that can measure the internal timing margin of receiver with only 1% area overhead. The prototype ICs are implemented using 0.18‐μm HVCMOS process and evaluated in an 8K 65‐inch panel.

Published
2023
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