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143 p., El objetivo general de esta tesis es investigar y proponer una arquitectura de referencia para sistemasSoPC que permita proteger tráfico IEC 61850 con requisitos de tiempo real de acuerdo al estándar IEC62351 en dispositivos SAS utilizados en redes Smart Grid. Consecuentemente, se proporcionaráconfidencialidad, integridad y autenticidad a los mensajes IEC 61850 con requisitos de tiempo real. Paraello, la arquitectura propuesta deberá abordar los estrictos requisitos temporales asociados a lageneración, protección, distribución y procesamiento de los mensajes GOOSE y SV definidos en elestándar IEC 61850. Adicionalmente, la solución propuesta deberá soportar altas tasas de transferencia dedatos, sin que el rendimiento se vea afectado. Finalmente, la arquitectura propuesta deberá hacer un usoreducido de los recursos lógicos del sistema SoPC, siendo este apartado un componente clave paragarantizar la viabilidad de la solución en SAS.

Ponencia presentada en XXXVIII Conference on Design of Circuits and Integrated Systems - DCIS 2023, November 15-17, 2023, Málaga, Spain., SpaceWire is a communication protocol that has become widely used in spacecraft for connecting instruments to data processors, mass-memory, and control processors. Field-Programmable Gate Arrays (FPGAs) have been a popular choice for implementing SpaceWire nodes due to their flexibility to meet unique requirements of each program or product. This paper presents a comparative study of two implementations of SpaceWire nodes, based on two different FPGA technologies, AMD-Xilinx SRAM-based and Microchip (Microsemi) FLASH based. The study compares the resource requirements and estimated power consumption of both implementations, using the same HDL SpaceWire IP core, with the SRAM-based one incorporating a 32-bit Microblaze soft-CPU, and the FLASH based one using a 32-bit RISC-V CPU. The obtained results are compared, and the paper concludes that FLASH-based FPGAs are more suitable for applications that require high reliability, tamper resistance, and fast, reliable restarts. In contrast, SRAM-based FPGAs are preferred in applications that require high performance and reconfigurability. The study shows that both FPGA technologies are capable of implementing SpaceWire nodes effectively and efficiently, and designers can choose the technology that best suits the specific requirements of each project.

Inferring faults throughout the power grid involves fast calculation, large scale of data, and low latency. Our heterogeneous architecture in the edge offers such high computing performance and throughput using an Artificial Intelligence (AI) core deployed in the Alveo accelerator. In addition, we have described the process of porting standard AI models to Vitis AI and discussed its limitations and possible implications. During validation, we designed and trained some AI models for fast fault detection in Smart Grids. However, the AI framework is standard, and adapting the models to Field Programmable Gate Arrays (FPGA) has demanded a series of transformation processes. Compared with the Graphics Processing Unit platform, our implementation on the FPGA accelerator consumes less energy and achieves lower latency. Finally, our system balances inference accuracy, on-chip resources consumed, computing performance, and throughput. Even with grid data sampling rates as high as 800,000 per second, our hardware architecture can simultaneously process up to 7 data streams.

Nowadays, system-on-chips have become critical since they support more and more safe applications due to their flexibility. However, they are susceptible to single-event upsets because the memory cell size has significantly shrunk. This article presents a triple redundant on-chip interconnect bus that provides low-speed peripherals with high reliability. In addition to correcting single errors and detecting duplicated ones, the proposed circuit offers zero latency and is transparent for both the embedded processor and the peripherals. These characteristics make it suitable for hard real-time applications. At the same time, the impact on area and power consumption is minimal.