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In this work, an ultra-low -jitter wideband cascaded local oscillation (LO) generator for 5G frequency range 1 (FR1) is presented. Using the phase-rotating divider (PRD) of the 2nd-stage ring-oscillator-based frequency multiplier (RO-FM) that can generate fractional multiplication factors ( ${M}\text{s}$ ), the required frequency-tuning range (FTR) of the 1st-stage phase-locked loop (PLL) dramatically decreased to 21%, which can be covered easily by a single low-phase-noise LC -voltage-controlled oscillator (VCO). Thus, the proposed LO generator can cover entire FR1 bands using only one LC tank. To suppress the fractional spurs caused by the mismatches of the delay cells of an RO, an individual-delay-cell-controllable digital loop filter (IDC-DLF) was used to calibrate the mismatches. Since the IDC-DLF equalizes the intervals between the quadrature signals of the RO, it can also naturally guarantee a precise quadrature relationship without any additional calibration. The 1st-stage PLL was designed based on a subsampling architecture, and it used a digital-to-analog converter (DAC)-based quantization error ( ${Q}$ -error) cancellation, dual-clock-phase generator, and a third-order curve fitting digital predistortion (TCF-DPD) to achieve ultra-low phase noise. The proposed LO generator was fabricated in a 65-nm CMOS process, and it used the power of 17.9 mW and the area of 0.64 mm2. The rms jitter, measured near 7.675 GHz ( $M = 4.25$ ), was 135 fs, and the calculated ${I}/{Q}$ phase error from the fractional spur level was 0.16°.