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The reconstruction of 4°off 4H-SiC surfaces was investigated using Si melting at 1550°C in a SiC/Si/SiC sandwich configuration. Despite systematically obtaining a macrostepped morphology over the entire areas in contact with the liquid Si, the steps were found wavy when using as-received 4H-SiC wafers. The regularity and straightness of the steps were significantly improved when the surface reconstruction was performed on processed surfaces: on re-polished surfaces the steps were found to be regular and straight in some cases, while this was constantly observed on as-grown epitaxial layers. After a reconstruction process of 2h, the best regularity of the steps was obtained with an average width of ̴ 3-5 μm. Increasing the processed area from 1.44 to 4 cm2 did not affect the results which suggests a good scalability of the process.

Current electronics technology increasingly demands higher integration, flexibility, higher efficiency, and performance aspects such as compatibility with higher temperature operation of the semiconductor devices, which may find limitations when silicon is used. The superior intrinsic properties of SiC, eventually combined with the ability of growing monolithically epitaxial, high quality graphene on a SiC wafer (1), makes it a reliable alternative for some electronic applications, such as field effect transistors (FET), radio frequency (RF) power amplifiers, integrated circuits (IC), or sensors. In this work, we describe the fabrication and preliminary electrical characterizations of epitaxial graphene (EG) on a SiC substrate FET devices based on an alternative back gate architecture. We propose a new approach in which the FET device is built on a 4◦ off-axis cut, N+ doped 4H-SiC substrate (the back gate) with, on top of, it a 1μm semi-insulating homoepitaxial layer of SiC compensated with vanadium (the dielectric layer). EG will be used as FET conduction channel. Using this V-compensated dielectric layer is aimed to minimize effects on the FET characteristics such as from defects in the SiC crystal, especially below the FET active areas, which would have occurred when using ion implantation to create a buried gate. The EG film was grown by the high temperature Si sublimation method under an Ar ambient. Raman spectroscopy, Atomic Force Microscopy (AFM) and Scanning Electron Microscopy (SEM) were applied in the structural characterization of epigraphene. The lack of D-peak in Raman spectra, together with SEM and AFM images, indicate that high quality monolayer to few layer epitaxial graphene fully covering the SiC surface is deposited. The electrical characteristics of the EG channel-devices and the functionality of the bottom gate were examined with 2-probe and 4-probe method. The electrical properties of the FET devices were also investigated with 3 terminal configuration.

Due to their low leakage current, low noise levels, high thermal conductivity, and potential radiation hardness, SiC devices offer various advantages over Si devices in certain applications. As a result, they are being considered for operation in harsh environments, such as plasma diagnostic systems in future nuclear fusion reactors or in high energy physics applications. We report on relevant results of the GRACE project, which seeks to deliver a new generation of SiC sensors with graphene-enhanced contacts. Such devices are aimed to be radiation-hard and functional at high temperatures. The work presented in this paper focuses on the optimisation of the electrical contacts, along with the electrical characterisation and radiation-tolerance assessment of the first sensor prototypes produced., This work was supported by the Spanish State Research Agency (AEI) and the European Regional Development Fund (ERDF), ref. RTC-2017-6369-3.