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For the first time, the flash sintering (FS) of high-purity alumina at room temperature, which was previously considered unachievable due to its low electrical conductivity, was conducted herein. The electrical arc originating from surface flashover was harnessed to induce FS at room temperature and low air pressure. The successful FS of high-purity alumina was realized at 60 kPa under the arc constraint, resulting in a notable relative density of the alumina sample of 98.7%. The electric–thermal coupling between the arc and high-purity alumina sample during the arc-induced FS process was analyzed via the finite element simulation method. The results revealed the thermal and electrical effects of the arc on the sample, which ultimately enhance the electrical conductivity of the alumina sample. The formation of a conductive channel on the sample surface, a result of increased electrical conductivity, was the pivotal factor in achieving FS in high-purity alumina at room temperature. The arc constraint technique can be applied to numerous materials, such as ionic conductors, semiconductors, and even insulators, under room-temperature and low-air-pressure conditions.

The MOSFET synchronous rectification (SR) is widely used to reduce the conduction loss during the freewheeling period. Due to the wide band gap of silicon carbide (SiC), the intrinsic body diode of SiC MOSFET exhibits a high voltage drop. Therefore, SiC Schottky diodes (SBD) and SiC MOSFETs are usually used in reverse parallel to reduce power loss. However, the increase of equivalent junction capacitance due to the addition of an external SiC SBD could bring larger turn-on current on opposite power transistor of the phase-leg. Furthermore, as the parasitic inductance associated with layout hinders the prompt transfer of current between SiC SBD and body diode, the external SiC SBD cannot be fully utilized, and it may deteriorate the overall performance, especially at heavy load. We comprehensively compare power losses when SiC SBD are antiparallel or not, at different working conditions, including different layout compactness, load current and dead time. It’s hard to get the effect of loss reduction loss when add antiparallel SiC SBD due to the parasitic inductance induced by the layout. The results can provide a guidance to properly select SiC SBD in a phase-leg configuration under SR mode for freewheeling during the dead time.

Oxygen vacancy OV plays an important role in a flash sintering (FS) process. In defect engineering, the methods of creating oxygen vacancy defects include doping, heating, and etching, and all of them often have complex processes or equipment. In this study, we used dielectric barrier discharge (DBD) as a new defect engineering technology to increase oxygen vacancy concentrations of green billets with different ceramics (ZnO, TiO2, and 3 mol% yttria-stabilized zirconia (3YSZ)). With an alternating current (AC) power supply of 10 kHz, low-temperature plasma was generated, and a specimen could be treated in different atmospheres. The effect of the DBD treatment was influenced by atmosphere, treatment time, and voltage amplitude of the power supply. After the DBD treatment, the oxygen vacancy defect concentration in ZnO samples increased significantly, and a resistance test showed that conductivity of the samples increased by 2–3 orders of magnitude. Moreover, the onset electric field (E) of ZnO FS decreased from 5.17 to 0.86 kV/cm at room temperature (RT); while in the whole FS, the max power dissipation decreased from 563.17 to 27.94 W. The defect concentration and conductivity of the green billets for TiO2 and 3YSZ were also changed by the DBD, and then the FS process was modified. It is a new technology to treat the green billet of ceramics in very short time, applicable to other ceramics, and beneficial to regulate the FS process.

Abstract In this study, we reported that flash sintering (FS) could be efficiently triggered at room temperature (25 °C) by manipulating the oxygen concentration within ZnO powders via a versatile defect engineering strategy, fully demonstrating a promising method for the repaid prototyping of ceramics. With a low concentration of oxygen defects, FS was only activated at a high onset electric field of ∼2.7 kV/cm, while arcs appearing on the surfaces of samples. Strikingly, the onset electric field was decreased to < 0.51 kV/cm for the activation of FS initiated, which was associated with increased oxygen concentrations coupled with increased electrical conductivity. Thereby, a general room-temperature FS strategy by introducing intrinsic structural defect is suggested for a broad range of ceramics that are prone to form high concentration of point defects.

Abstract The development of ultra‐high voltage transmission lines requires a ZnO arrester with excellent electrical response and high voltage gradient. Compared with conventional preparation methods, flash sintering allows fast production of novel high‐performance ZnO varistor ceramics with low energy consumption and controlled grain growth. Herein, ZnO varistor ceramics were prepared using the flash sintering method at an air pressure of 21 kPa for 60 s at 25°C. The results showed that the flash‐sintered samples had fine grains and reduced loss of volatile elements. Moreover, the voltage gradient, leakage current density, and non‐linear coefficient of the flash‐sintered varistor ceramics were significantly improved compared with those of conventionally sintered samples. Owing to the short preparation time and absence of a heating process, the energy consumption of the proposed flash sintering method was significantly reduced to 10% of that by conventional sintering. The proposed method is a promising approach for the preparation of ZnO arresters with excellent electrical properties and serves as an effective method that realises energy saving and emission reduction.